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Keysight Design Engineering Software at DAC 2026
Visit us at Booth #927
July 26th - 29th
Long Beach, CA
Book a Meeting at the Keysight Booth #927
To schedule a meeting and/or demo with Keysight at DAC, select an available day and time on the calendar to learn more about one or more of our Design Engineering Software solutions:
- Advanced Packaging for Chiplet, 3DIC, and 3DHI
- AI-Driven Validation & Design Data Intelligence
- AI-Driven Workflow Automation
- High-Speed Digital Standards and CPO/E-O-E
- Multi-Physics Engineering Workflows
- RTL Power Analysis & Optimization
- SOS AI - MLOps, Agentic Workflows, and Strategic Decision Support
- SOS Enterprise for Organizational Memory and AI-Readiness
Meetings and demos are available on these days and times:
- Monday, July 27, 10:00 am – 6:00 pm
- Tuesday, July 28, 10:00 am – 6:00 pm
- Wednesday, July 29, 10:00 am – 4:00 pm
I LOVE DAC 2026 Promotion
Keysight is proud to be an I LOVE DAC Sponsor and DAC Silver Sponsor. We're excited to exhibit live at DAC 2026 booth #927. Click the button below and register today for free before the registration ends using the I LOVE DAC registration.
Don’t Miss Our Technical Sessions to Go Deeper Into Keysight Design Engineering Software Workflows and Real World Use Cases.
From Bit to Qubit: EDA Meets Quantum
This session highlights practical, engineering‑oriented approaches to quantum computing, showcasing real-world tools such as quantum EDA platforms and digital twin solutions. It explores how quantum concepts intersect with chip design workflows and what engineers need to understand now to stay relevant as the field evolves.
- Date: Monday, July 27, 2026
- Time: 3:30 PM - 5:00 PM PDT
- Location: Seaside Room 7
Chris Mueth
Senior Director, New Markets and Strategic Initiatives
Ian Rippke
Director Global Software Solutions
AI at the RF Frontier: De-Risk and Accelerate Next-Gen Custom RF/MW Design
AI‑driven techniques are reshaping RF and microwave design through surrogate modeling, automation, and digital twins. This session presents real‑world case studies showcasing multiphysics co‑design, advanced optimization, and closed‑loop validation for wireless and defense systems.
- Date: Tuesday, July 28, 2026
- Time: 10:30 AM - 11:00 AM PDT
- Location: Exhibitor Forum, Exhibit Floor
A Mixed-Domain Modeling Approach for Hatched Ground Planes in 3D Chiplet Die-to-die Interconnect
Advanced chiplet based packaging increasingly relies on patterned ground planes, introducing new SI/PI challenges. This paper presents a scalable mixed domain modeling approach that combines quasi static and full wave solvers, validated through silicon bridge and mobile PCB test vehicles, enabling accurate and efficient interconnect analysis for advanced packaging designs.
Presenters: Dr. Tim Wang Lee, HeeSoo Lee, Keysight | Orlando Bell, Gigatest Labs
- Date: Monday, July 27, 2026
- Time: 5:00 PM - 6:00 PM PDT
- Location: DAC Pavilion, Exhibit Floor
Dr. Tim Wang Lee
Signal Integrity Application Scientist
HeeSoo Lee
High-Speed Digital Segment Lead
AI-Enabled High-Fidelity Power Amplifier Behavioral Modeling with Commercial EDA Tools
This paper presents an AI‑based methodology for developing high‑fidelity power amplifier behavioral models using Keysight SystemVue and ADS. A neural‑network model is trained using co‑simulation data, achieving high accuracy while capturing transient behavior across a wide power range. The resulting model integrates seamlessly into system‑level simulations for performance verification and design.
Presenter: Fei Cao
Authors: Ziquan Bai, Yanhua Cui, Lei Li, Tong Li
- Date: Monday, July 27, 2026
- Time: 5:00 PM - 6:00 PM PDT
- Location: DAC Pavilion, Exhibit Floor
Fei Cao
R&D Senior Manager
Machine Learning Optimizer-Driven Automatic Full Compact Model Extraction Flow Development
As compact models increase in complexity, traditional manual extraction flows become time consuming and prone to sub optimal convergence. This paper introduces an ML driven, Python based optimization framework that decomposes global model extraction into structured stages, enabling scalable and repeatable parameter extraction. Results on GaN HEMT and production grade models demonstrate hours level turnaround with accurate IV/CV correlation, significantly reducing reliance on expert tuning.
- Date: Wednesday, July 29, 2026
- Time: 3:00 PM - 3:45 PM PDT
- Location: DAC Pavilion, Exhibit Floor
Fahad Usmani
Device Modeling Product Planner
Maximize ROI Through Glitch Power Optimization at Early Design Stage
At advanced process nodes, glitch activity can account for up to 25% of dynamic power. This work presents an RTL level glitch analysis and optimization methodology that enables early detection and mitigation, achieving 10-30% dynamic power reduction and significantly higher ROI than late stage fixes.
Presenter: Awashesh Kumar, R&D Engineer
Authors: Abbin Perunnilathil Joy, Christina Farran
- Date: Wednesday, July 29, 2026
- Time: 3:00 PM - 3:45 PM PDT
- Location: DAC Pavilion, Exhibit Floor
Awashesh Kumar
R&D Engineer
Hunting RTL Glitches Before They Burn Power: A Practical RTL Success Story
This paper introduces a data driven RTL glitch analysis methodology that enables early identification and mitigation of high impact glitch power using delay aware propagation.
Presenter: Suhail Saif, Product Marketing Manager
Authors: Zhongming Hou, Keysight |Xiaobing Tang, Ling Sun, Shixuan Que ,Fengyu Xiao, Wanyan Ji, Iluvatar
- Date: Wednesday, July 29, 2026
- Time: 3:00 PM - 3:45 PM PDT
- Location: DAC Pavilion, Exhibit Floor
Suhail Saif
Product Marketing Manager
An Executable RF Design Workflow Whiteboard
Nexus Connect captures the complete design methodology, immediately deploys it in customized workflows with simulation and optimization, and visually documents each workflow. Work visually on an executable whiteboard flowchart or programmatically in Python. Read this Solution Brief to get started.
SOS Enterprise: Govern at Scale
Go beyond SOS Core and start using SOS Enterprise today!
Governance That Actually Works
Complete audit trails. Role-based access control. Compliance-ready reporting. Your team finally gets the visibility they've been demanding. Managers get answers in minutes, not weeks.
Global Scale, Zero Compromise
Teams in multiple time zones working on the same designs without conflicts. Distributed repositories that feel local. Performance that doesn't degrade when you cross borders.
AI-Ready Engineering Data
Clean, structured, traceable data ready for machine learning and AI-driven design tools. Your data becomes training fuel for the intelligent systems transforming our industry.
Build, analyze and optimize your quantum chips quickly, reducing your time to market.
Powering the Future of Superconducting Quantum Computing
Keysight EDA tools enable your team of quantum hardware engineers to streamline their workflow and accelerate the development of quantum chips using a cost-effective electromagnetic simulation approach based on the method of moments. Our state-of-the-art nonlinear circuit solver delivers extensive analysis of the power-dependent performance of your quantum chips, giving you unparalleled insights.
Chiplet 3D Interconnect Designer: Design and Optimize Chiplet Die-to-Die Channels in ADS
Chiplet 3D Interconnect Designer provides a fast and accurate design environment for die-to-die interconnects on silicon and organic bridges or interposers. It allows package and interconnect engineers to explore architectures and optimize interconnect channels before committing to a full package layout.
Key capabilities
- Physical channel design and optimization for chiplet interconnects
- Support for hatched and waffle ground planes
- Standard-driven bump maps for UCIe and BoW
- Fast mixed-domain channel modeling for early design exploration
- Guided, user-friendly design workflow
- Direct integration with Chiplet PHY Designer