Join us for a networking seminar with our Keysight PCIe 5.0, DDR5, Simulation experts, and others in your field. We’ll provide lunch, demos and conversation with industry experts.

This hands-on seminar will cover test and validation methodologies, with best practice examples, to help PCIe 5.0 and DDR5 technology adopters fully test all key measurement parameters to ensure their design meets the specification requirements. Learn the following:

  • Evolution of PCIe and DDR technologies
  • PHY Layer testing challenges at 32 GHz NRZ and 64 GT/s
  • Looking forward to PAM4 technologies
  • TX and RX test solutions for PCIe 5.0 and DDR5 Devices
  • Simulation and verification environments
  • New requirements for DDR5 simulation

AGENDA

9:00 a.m. – Registration and Refreshments
9:30 a.m. – PCIe 5.0 and Beyond
11:30 a.m. – Working Lunch / Simulation of DDR5 Memory Designs
12:30 p.m. – DDR5 – Design and Test Challenges
1:30 p.m. – Q&A and Wrap-up / Prize Giveaway
2:00 p.m. – Demos

DATE/TIME/LOCATION

This event will be rescheduled to a later date, due to COVID-19.

CO-SPONSOR

Keysight’s Experts

Rick Eads

Principal PCI Express Program Manager

Director, PCI-SIG Member, PCISIG Electrical Work Group (EWG), Card Electromechanical Work group (CEG), Serial Enabling Work Group (SEG)

Co-Chair: GenZ Compliance and Interoperability work group

Perry Keller

Digital Standards and Applications Program Lead

Memory Program Manager
JEDEC Board of Directors
Chairman, JC40.5, JC45.5, and JC64.5 Validation Committees

Stephen Slater

Product Planning and Marketing Manager for SI / PI Simulation Software

Keysight PathWave Software Solutions 
Member of SI Journal Editorial Advisory Board

Have questions or need help?