Data Sheets
The Keysight Technologies, Inc. FPGA dynamic probe provides greater real-time measurement productivity for logic analysis based validation of FPGAs and the surrounding system. The tool features:
Q1 How do I create an ATC2 core?
Xilinx ChipScope Pro or EDK provides the capability to create an ATC2 core. You need Xilinx ChipScope Pro or EDK to create the ATC2 core and to merge it with your design. Using either of these tools, you can specify the parameters of the ATC2 core and specify which design signals go to the ATC2, making them available for real-time measurement.
Q2 How do I get an ATC2 core into my design?
Xilinx ChipScope Pro includes Core Inserter and Core Generator. Core Inserter puts the core into your FPGA design post synthesis. Keysight Technologies, Inc. recommends using Core Inserter. If you use Xilinx Core Generator or EDK, the tool instantiates your parameterized ATC2 as a black-box Verilog or VHDL unit. The synthesis tool puts the instantiated core into your design during the synthesis process.
Q3 What synthesis tools can I use to get the ATC2 core into my design?
ATC2 cores produced by Xilinx Core Generator or EDK are compatible with:
Q4 Are there advantages to using Core Inserter versus Core Generator or EDK?
Yes. Core Inserter also produces a .cdc file. This is a small file listing the signal inputs to the ATC2 core. This file is used to automatically synchronize design signal names with logic analysis bus and signal names. Keysight recommends using Xilinx Core Inserter so you can take advantage of signal-name mapping. Xilinx has a stimulus core known as VIO. This core can only be created and placed in a design using Core Generator. For a single design that contains both a VIO core and an ATC2, Core Generator must be used.
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