IIT Delhi Professor Automates Reliability Characterization

Organization

• Indian Institute of Technology, Delhi

Challenges

• Characterization of RF complementary metal-oxidesemiconductor (CMOS) from mid- to high-frequency devices and circuits.

• Complex and manual involvement for DC and  RF measurements that  are sometimes prone to  human error.

Solutions

• Keysight’s B1500 semiconductor device parameter analyzer / semiconductor characterization system with network analyzer and probing station.

Results

• Integrated setup to perform stress / measure / stress cycles for “n” number of hours; “n” not a constraint.

• Use case applications; 5G, Wi-Fi 6, and more.

Semiconductor technology continues to evolve, time-to-market cycles are shrinking, and the need for even greater accuracy is increasing. Over the years, integrated circuits have been moving towards miniaturization with overall performance improvement. The increasing demand is due to the requirement of a compact form factor or decreased product size.

Many of the latest products must accommodate multiple technology chips that include a considerable amount of space for batteries. But it is not only about the size. The industry is also looking for higher performance, efficiency, and advanced specifications in accuracy, speed, and more. These designs require integrating millions of transistors and other components ready for test without any scope for error.

Instead of running tests for multiple days, the goal is to reduce the test duration while accommodating all scenarios which might affect the devices over time. The dense circuits also require various test parameters — multiple test tools and different combinations of test scenarios can make it complicated. Spending too much time on test and validation rather than the design and debug process is not efficient.

The Organization

Professor Abhisek Dixit leads the device and wafer-level modeling and characterization group at the Indian Institute of Technology, Department of Electrical Engineering, located in New Delhi, India. This group’s focus is reliability characterization and process design kit (PDK) modeling of complementary metal-oxide-semiconductor (CMOS) devices and circuits. His team is actively pursuing reliability characterization of advanced CMOS devices and circuits fabricated by various global industry collaborators. 

The Challenges

The importance of reliability for digital CMOS operation where stressing fields for DC or AC in very high frequency (VHF) / ultra-high frequency (UHF) / L / S bands is critical. Routine techniques exist to measure reliability components, such as the hot-carrier stress, bias temperature instability, and timedependent dielectric breakdown.

However, in RF CMOS circuits operating in the frequency range of  6 to 7 GHz for Wi-Fi and 28 GHz for 5G and beyond technologies, stress is often due to high-frequency RF signals. Degradation is a time-dependent phenomenon that affects carrier trapping / de-trapping, interface state generation, and more.

A measurement setup is necessary to characterize these new RF reliability effects to enable:

• Applications for several types of stress voltages — DC, pulse, and RF control for the stress test duration, periodic termination, and resumption at specific time intervals.

• Measurements of the DC, IV, small, and large-signal RF performance in the time window between successive stress cycles.

• Delays your measurement with precise control