B4655A FPGA Dynamic Probe for Xilinx

B4655A FPGA Dynamic Probe for Xilinx

Data Sheets

The Challenge

You rely on the insight a logic analyzer provides to understand the behavior of your FPGA in the context of the surrounding system. A typical approach is to take advantage of the programmability of the FPGA to route internal nodes to a small number of physical pins that a logic analyzer can measure. While this is a very useful approach, it has significant limitations.

  • Since pins on the FPGA are typically an expensive resource, there are a relatively small number available for debug. This limits internal visibility (i.e. one pin is required for each internal signal to be probed).
  • When different internal signals need to be accessed you must change your design to route these signals to pins. This can be time consuming and can affect the timing of the FPGA design.
  • Finally, the process required to map the signal names from the FPGA design to the logic analyzer setup is manual and tedious. When new signals are routed out, the need to manually update these signal names on the logic analyzer takes additional time and is a potential source of confusing errors.

 

A Better Way

Collaborative development between Keysight Technologies, Inc. and Xilinx have produced a faster and more effective way to use your logic analyzer to debug FPGAs and the surrounding system. The Keysight FPGA dynamic probe, used in conjunction with an Keysight logic analyzer, provides the most effective solution for simple through complex debugging.

 

Debug Your FPGAs Faster and More Effectively with a Logic Analyzer

The Keysight FPGA dynamic probe, used in conjunction with a Keysight logic analyzer, provides the most effective solution for debugging problems [simple through complex]. The FPGA dynamic probe lets you:

  • View internal activity — With a logic analyzer, you are normally limited to measuring signals at the periphery of the FPGA. With the FPGA dynamic probe, you can now access signals internal to the FPGA. You can measure up to 128 internal signals for each external pin dedicated to debug, unlocking more visibility into your design than you ever had before.
  • Make multiple measurements in seconds — Moving probe points internal to an FPGA used to be time consuming. Now, in less than a second, you can easily measure a different set of internal signals — without design changes. FPGA timing stays constant when you select new sets of internal signals for probing.
  • Leverage the work you did in your design environment — The FPGA dynamic probe is a tool that maps internal signal names from your FPGA design tool to your logic analyzer. Eliminate unintentional mistakes and save hours of time with this automatic setup of signal and bus names on your logic analyzer.

 

Measurement setup step 1: Establish a connection between the analyzer and the ATC2 core

The FPGA dynamic probe application establishes a connection between the logic analyzer and a Xilinx cable. It also determines what devices are on the JTAG scan chain and lets you pick the device with which you wish to communicate. Core and device names are user definable.

 

Measurement setup step 2: Map FPGA pins

Quickly specify how the FPGA pins (the signal outputs of ATC2) are connected to your logic analyzer. Select your probe type and rapidly provide the information needed for the logic analyzer to automatically track names of signals routed through the ATC2 core.

 

For ATC2 cores with auto setup enabled, each pin of the ATC2 core, one at a time, produces a unique stimulus pattern. The instrument looks for this unique pattern on any of its acquisition channels. When the instrument finds the pattern, it associates that instrument channel with the ATC2 output pin producing it. It then repeats the process for each of the remaining output pins eliminating the need to manually enter probe layout information.