PathWave Advanced Design System (ADS) 2021 Update 2.0 Product Release

PathWave ADS 2021 Update 2.0 is available now!

New capabilities in PathWave ADS 2021 Update 2.0 include:

Platform

• Unarchive command is improved to skip over any libraries that have problems
• cds.lib file is supported for workspace library definition for improved interoperability with Cadence Virtuoso
  

Data Display

• Pictures can be inserted to a Data Display page as an image or an expression
• Datalink is upgraded to use python 3.8.5 and contains the pwdatatools package for processing measured and simulated data in any format
• DDS Palette and combo box for listing dataset are re-sizable
• Drag and drop operations can be performed from the Expression Manager
  

Layout

• Physical connectivity engine now supports instance arrays
• OA Path is supported to improve the ADS interoperable flow
• VIA / Teardrop transition notches in ground planes are automatically removed
• Area pins can be assigned to Padstacks and Vias without pre-existing pins needed
• Layout versus Layout (Circuit Comparison)
• New ODB++ Export for version 8 with nets, components, and stack-up to facilitate sharing minor layout edits with original enterprise PCB layout tool
• ODB++ import bug fixes including better handling of polygons with holes
  

RFPro EM simulation

• Can simulate impact of thickness bias of dielectrics and conductors
• A 3D metal can now fill a dielectric without needing vias
  

Circuit Simulation

• New Corana algorithm in Simulated Annealing optimization to find global minimum amongst extremely numerous local minima

Electrothermal

• Cross-plane > in-plane conductivity is now supported (the reverse already was)
• Allow arbitrary reduction of domain bounds
• Annotate entire device’s temperature (I.e., not just transistor fingers) in dataset
  

High Speed Digital - SerDes

• ADS COM calculation supports COM Version 2.93, and Batch Simulation
• Smart eye probe supports eye mask measurement
• Improved S-Parameter Checker usability including easier port set up, NEXT, and FEXT measurements
• ADS FlexDCA probe supports differential signal from single-ended eye probe for FlexDCA compliance test measurements
• Improved multi-lane Channel Sim Batch Simulation with an example
• Eye probe/Diff_Eye Probe component can now recognize PAM4_PRBS component in the name of ‘source list’ for Transient Simulation

High Speed Digital - DDR/Memory

• SIPro - New DDR analysis type (Beta Feature) – significantly speeds up simulation by 2 to 4x
• New Memory Interface AMI Model for DDR5 and LPDDR5 AMI model generation in ADS
• Memory Designer now supports new DRAM type, GDDR6 solution
• Supports integrated IBIS-ISS (Interconnect SPICE Subcircuit) model in DDR Controller/Memory components
• Improved IBIS model editor grouping, that now allows you to add and remove signals from model group in DDR Controller/Memory
• Supports multi-threading in Memory Probe for speeding up measurements
• Facilitates easy access to the S-Parameter TDR Front Panel in DDR PCB
• Improved package model setup for touchstone file with header information, by automatic IBIS pin assignment
• Improved DIMM connector setup for touchstone file with header information, by automatic signal property assignment
• Memory Designer now supports custom mask entry in Memory Probe
• Improved usability for Design Exploration, no need to use "Set" button to set the limits from the Memory probe dialog box

Power Integrity

• PIPro AC now supports parallel simulations and PathWave Design Cloud Sim Service for high performance computing

Power Electronics

• Power Electronics Model Builder tool enhancements
• Surface Current Density visualization on inner layers in PEPro