GaN Power Devices: Design Environment Benefits

GaN Power Devices are Becoming Broadly Available, with Steady Progress in Design Environment in Addition to Secure Reliability

The benefits of GaN power devices are clear: fast switching speeds at high frequencies and low power loss. Such benefits enable power supply circuits to be dramatically smaller in size and more efficient in power conversion.

Another piece of good news is that their availability has significantly improved over the past year. A few manufacturers have already commercialized GaN power devices so that users can purchase and examine the devices.

The conditions for the GaN power device market to expand seem to have been fulfilled in various respects. Despite the clear advantages mentioned above, there are still some critical issues left unsolved.

It is still a challenging job to replace Si power devices with GaN power devices, as their reliability, robustness, and ease of design need to be the same as those of Si power devices. This article introduces the efforts made by Panasonic to solve such issues.

Beyond JEDEC

Panasonic launched two 600 V blocking voltage GaN power transistors: PGA26E19BA with 140 mΩ of on-resistance at 13 A of drain current, and PGA26E07BA with 56 mΩ of on-resistance at 26 A of drain current.

A six-inch Si wafer has been adopted as the substrate. AlN and AlGaN layers are layered on the substrate, and over all this, a GaN epitaxial layer is formed. The issue here is the difference between the thermal expansion coefficients of Si and GaN.

In the process of forming the epitaxial layer, the entire substrate is heated, and then cooled down instantaneously, which causes stress in the epitaxial layer, introducing cracks. Such cracks make the device useless.

To solve this issue, Panasonic inserts a buffer layer, which is an artificial lattice in which GaN layers and AlN layers are alternately stacked, beneath the GaN epitaxial layer. This reduces the stress, and consequently prevents cracks in the GaN epitaxial layer.

The developed GaN power transistors perfectly pass the reliability tests for power devices defined by JEDEC (Joint Electron Device Engineering Council). But, that does not necessarily prove that their reliability and robustness exceed those of Si power devices.

Panasonic argues that the tests defined by JEDEC are not adequate to demonstrate the reliability and robustness of GaN power transistors, and that it is essential to make efforts for Beyond JEDEC, which aims for tests whose limits are stricter than those defined by JEDEC.

Normally-Off GaN Devices Realized By Applying Innovative Structures

Panasonic’s two products have already leveraged the outcomes of Beyond JEDEC. Panasonic has made multiple efforts, two of which are introduced below.

The first one was to realize normally-off GaN power transistors. Simply attaching a gate electrode makes a transistor normally-on.

Normally-on is not acceptable for applications in power supplies because current in the device keeps flowing even if the power supply fails, which will likely cause fires or other disasters. Panasonic improved the electrode structure, using a creative way of sandwiching p-type GaN layer between the gate electrode and GaN epitaxial layer.

When the device is turned off, the depletion layer expands in the channel and shuts off the drain current, which makes the device normally-off. This structure is called a gate injection transistor (GIT).

The second one was to take measures to prevent current collapse. Current collapse generally increases the dynamic on-resistance of GaN power transistors, accelerating heat generation, which shuts the power supply down.

Today, the mechanism of current collapse is understood as follows. There are still some stresses caused by the difference in the thermal expansion coefficients in the GaN epitaxial layer, causing dislocation.

When voltage is applied in such a situation, highlycharged electrons are trapped by the dislocations, preventing the flow of drain current. Thus, the dynamic on-resistance increases.

Two measures were taken to solve the problem. The first one was to optimize the process of forming epitaxial layers and to optimize the artificial lattice buffer layers. This measure alone, however, cannot prevent an increase in on-resistance when the blocking voltage exceeds 600 V.

Thus, a second measure was taken, which was to inject holes to recombine the holes with the trapped electrons, and thus eliminate the trapped electrons (Figure 3). In practice, a second drain electrode, whose structure is same as the gate electrode, is set next to the drain electrode, and holes are injected through the second drain electrode.

This structure is called a hybrid drain embedded GIT (HD-GIT). By combining these two measures, Panasonic says, “the current collapse problem is completely solved for up to 850 V of blocking voltage.”

Consequently, the GaN power transistors commercialized by implementing these measures fulfill even test requirements for reliability and robustness that are not defined by JEDEC.

For instance, the transistors demonstrate no increase in on-resistance due to aging, and have achieved over 3,600 hours in the dynamic high temperature operating life (D-HTOL) test, which means that they are ready to replace Si power devices also in terms of reliability and robustness.

Also Proceeding With Development of Design Environment

The remaining challenge is to raise the ease of design. GaN power transistors have extremely high performance, and their switching speed is as high as tens of megahertz, which is almost impossible for Si power devices to achieve.

Not all engineers, however, can benefit from such high performance. It requires high skills and varied experience in power supply design and PCB (printed circuit board) design.

For example, patterns that are too long on a PCB may increase parasitic inductance, which prevents the circuitry from driving the devices at high frequencies.