Scale-Up ESUN/UE Interop

Validate multi-vendor interoperability across ESUN and Ultra Ethernet scale-up networking technologies. Explore Link Layer Retry (LLR) and Credit-Based Flow Control (CBFC) validation on 100G and 200G SerDes.

PCIe® 7.0 Test Solutions

Explore Keysight’s PCIe® 7.0 test solutions and discuss your validation requirements with our experts.

Scale-Out MRC over SRv6

See MRC traffic running over an SRv6-based multi-path fabric, and examine how congestion within the fabric affects scale-out AI network performance.

AI Inference at Scale

Pinpoint bottlenecks with realistic AI inference workloads at scale against a live inference stack. Correlate workload performance with compute, GPU, memory, and network telemetry in a unified view to speed analysis and optimize the inference stack.

Scale-Across with Collectives

Explore the resiliency and performance of mixed collective workloads over a lossy scale-across network.

High-Density 1.6T AI Tester

Explore Keysight’s 1.6T Ethernet test portfolio, including the new SERT-1600GE and AresONE-Plus-1600GE platforms. See high-density testing with eight ports of 1.6T Ethernet in a single 2U appliance and stateful, realistic AI workload generation, including Mix-of-Collectives (MoC) emulation.

Take a Closer Look in a Private Meeting

Meet with Keysight experts in two dedicated suites at the San Jose Marriott, connected to the convention center. Choose the discussion that fits your next deployment.

Performance Validation of 1.6T Interconnect with FITS 16CH

Explore the expansion of the Keysight FITS portfolio to 16 channels. Discuss digital-layer bit error ratio (BER) and forward error correction (FEC) performance validation across active and passive copper interconnects, including active electrical cables (AEC) and direct attach copper cables (DAC), for 1.6T AI data center deployments.

Get UALink Ready

Explore Keysight’s UALink interoperability solution for AI scale-up networking. Meet with our experts to discuss your UALink validation requirements and readiness plans.

Book a Meeting

Learn with Keysight and Industry Experts

Join five technical sessions spanning AI infrastructure validation from design and pre-silicon through deployment, with perspectives from Keysight, NVIDIA, Meta, and Alibaba Cloud.

Schedule note: Session times and locations are subject to change. Check the conference agenda before attending.

AI Infrastructure Validation at Scale

Monday, October 12 | 12:00 p.m. – 12:20 p.m. | Concourse Level, Room 211

Speaker: Ram Periakaruppan, Keysight

Explore full-lifecycle system validation, from design and pre-silicon through post-silicon and deployment. Learn how realistic AI workloads help expose performance bottlenecks and address interoperability and system-level conformance.

Beyond Physical Digital Twins: Why Logical Digital Twins Are Essential for AI Factory Design, Validation, and Operations

Tuesday, October 13 | 2:05 p.m. – 2:25 p.m. | Concourse Level, Room 220B

Speakers: Avi Alkobi, NVIDIA; Abhijit Lahiri, Keysight

Explore how logical digital twins emulate compute, networking, storage, security, and workloads to validate AI factory architectures before deployment. See how workload-aware simulation can inform infrastructure sizing and deployment readiness.

Validation Methodologies for ESUN Ecosystem

Wednesday, October 14 | 8:50 a.m. – 9:10 a.m. | Concourse Level, Room 220B

Speakers: Manoj Wadekar, Meta; Venkat Pullela, Keysight

Examine validation challenges for ESUN-based scale-up AI networks, including lossless transport, latency, and multi-vendor interoperability at 800GE and 1.6T speeds. Explore benchmarking approaches for comparing ESUN implementations.

Standardizing Ethernet Scale-Up Validation: Test Strategy and Current Progress on LLR/CBFC

Thursday, October 15 | 9:45 a.m. – 10:00 a.m. | Concourse Level, Room 210AE

Speakers: Haiyang Zheng, Alibaba Cloud; Yuanwen (Daisy) Sun, Keysight

Learn about a vendor-neutral scale-up test standard for lossless, low-latency Ethernet AI fabrics, including tests for LLR and CBFC behavior to support predictable performance and multi-vendor interoperability.

Cluster-less Validation of AI Accelerator Silicon Under Real Workloads

Thursday, October 15 | 12:55 p.m. – 1:15 p.m. | Concourse Level, Room 220B

Speakers: Matt Bergeron, Meta; Ashutosh Kumar and Cosmin-Nicolae Prunaru, Keysight Technologies

Explore how to validate AI accelerator chips against realistic distributed-training workloads without a large physical cluster. Learn how emulating cluster behavior and replaying training communication patterns can help identify chip-level bottlenecks and defects earlier.

Continue the Conversation After Hours

Join the Keysight team on Day 3 for a casual evening of dinner, drinks, and trivia.

Connect with peers and continue the day’s conversations about AI infrastructure.

Let's Solve What's Next.

Talk to an expert who knows what it takes.

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Keysight at OCP Global Summit 2026