How to Evaluate FEC Performance for High-Speed Ethernet Links

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UXR-Series Oscilloscope
+ UXR-Series Oscilloscope
UXR-Series Oscilloscope
+ UXR-Series Oscilloscope

Validating FEC performance of high-speed Ethernet links

Testing high-speed Ethernet links requires evaluating the error-correction mechanism you are using. The process involves identifying the cause of the errors, which can either be forward error correction (FEC) symbol errors or PCS lane errors generated by port electronics, optical transceivers, or cables. Measurements like pre-FEC bit error rate (BER), FEC symbol density, the number of uncorrectable FEC codewords, and the frame loss ratio are used to determine link health.

The test setup for validating FEC performance of high-speed Ethernet links includes the device under test and a bit error rate tester (BERT) to replace some of the stressed lanes. An optical loopback goes from the device under test to an optical transceiver, but as an alternative, you can use an electrical loopback to the coax interface. For debugging purposes, use a real-time oscilloscope.

FEC analysis solution

High-speed Ethernet links introduce new challenges, including an increased bit error rate (BER), mandatory forward error correction (FEC), PCS performance issues, and different switch designs and implementations. The Keysight high-data-rate, multiple-channel FEC test solution provides test coverage for a broad range of Layer 1–3 use cases and visibility into all Ethernet lanes to detect and correlate meaningful errors.
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