P5551A PCI Express Protocol Exerciser for PCIe 5.0

Introduction

P5551A PCIe 5.0 Protocol Exerciser allows test engineers to emulate both PCIe root complex and endpoint devices when validating PCIe designs. The exerciser supports traffic generation from 2.5 GT/s through 32 GT/s and lane widths from x1 to x16. The tool includes over 100 built-in LTSSM test cases, error insertion capability at the TLP and DLLP layer, and an included protocol checker.

Product Overview

The Keysight P5551A PCIe 5.0 Protocol Exerciser provides test and validation engineers a powerful tool for vetting and debugging their PCIe designs. The P5551A uses an integrated, single add-in-card design which greatly simplifies the connection and setup of the tool while offering greatly improved signal integrity compared to other architectures. This enables test and validation engineers to focus their time and energy on designing and automating unique test cases for their products, rather than wasting time dealing with an overly complex test setup with poor signal integrity. 

The foundation of the P5551A is the improved signal integrity provided through the integrated design of the Exerciser card which provides a solid, trustworthy test platform. This compact design allows Keysight engineers great versatility in ensuring that the P5551A would have signal integrity characteristics that could be configurable enough to be tuned for many different test environments, while also offering quick link up capability for test cases that focus on higher layer protocol debugging. 

The P5551A Exerciser supports PCIe speeds from 2.5 GT/s up to 32 GT/s and Lane widths from x4, x8 and x16 along with the following features: 

• Follows all PCIe 5.0 electrical specifications. 

• Automated link training to 32GT/s

• Ability to initiate Higher and Lower Speed Changes between 2.5GT/s to max supported speed. • PCIe 5.0 link training bypass supported

• Traffic generation directly from GUI or from automated user generated scripts. 

• Lane Reversal and polarity detection

• Scalable flow control supported 

• Control of the Link Training and Status State Machine (LTSSM) operation

• Lane and Speed Negotiations from 2.5 GT/s to 32 GT/s. 

• Real Time Equalization process

• Transaction Layer Generation (Memory Read/Write, IO Request, Config Request)

• Error Insertion via NAK, Completion Error, DLLP Errors

• Emulate either upstream (Root Complex) or downstream (Endpoint) ports

Combined Exerciser and Analyzer Software

Both the Keysight P5551A PCIe 5.0 Protocol Exerciser and its companion tool, the P5552A PCIe 5.0 Analyzer, are supported by a single combined software interface, offering the user easy access to all of the powerful capabilities of both tools. Through a simple, tab based interface, the user can configure the Exerciser and Analyzer side by side with just a few clicks. The Exerciser GUI provides deep functionality for configuring Traffic Setup, while also providing improved data exchange with the analyzer.

Backplane Test Platform

Even more test setups can be created using the P5551A Exerciser along with the Keysight P5563A PCIe 5.0 Protocol Backplane Test Platform. The P5563A Test Platform features SI enhancements to reduce crosstalk and improve signal integrity, where low-loss material in utilized in order to support reliable connections at 32 GT/s.

• CEM form factor for endpoint devices. Automated link training to 32 GT/s

• Integrated low noise power supply with Auxiliary PCIe power available for high power endpoint devices

• Stable mechanical construction for reliable operation during bring-up

• One pair of CEM slots for connecting the Exerciser with a DUT.