Pre-Silicon Side Channel Analysis on Rambus AES Design
Case Studies
This case study demonstrates how Inspector Pre‑Silicon Side‑Channel Analysis enables early detection of side‑channel vulnerabilities at RTL and gate‑level using simulation‑based analysis.
By applying Test Vector Leakage Assessment (TVLA) to a Rambus AES design, Inspector Pre‑Silicon SCA successfully identified a previously known vulnerability in a pre‑release implementation and accurately pinpointed its root cause.
The results closely match traditional FPGA‑based validation while providing deeper signal‑level visibility and faster design iteration, allowing teams to validate the effectiveness of side‑channel mitigations before tape‑out, without requiring physical hardware.