How to Analyze Signal Integrity Using Layout Geometry
Demos
Moving printed circuit board (PCB) designs from layout to prototype requires verifying each PCB electrical trace for signal integrity (SI) compliance with a wide range of performance specifications. Learn how to use layout geometry to produce SI metrics such as trace impedance and delay, return and insertion loss, S-parameter analysis, and impedance time-domain reflectometry (TDR), to catch issues earlier and reduce the rounds of verification with SI specialists.