As silicon CMOS technology continues its relentless scaling into the nanometer regime, new device model frameworks are being introduced, and innovative model extraction methodologies are required to deliver a number of modeling capabilities that have morphed from good-to-have to must-have as their importance continues to rise.

Continued scaling of supply voltage, albeit somewhat slowed down in the cutting edge technologies compared to older technologies, and the non-scalability of threshold voltage in combination imply that the transistor will be operating mostly in the moderately super-threshold regions. As a result, accurate simulation-to-measurement fitting in the transition region is increasingly important. Newly developed model frameworks based on surface potential instead of threshold voltage formulation bring in an improved solution, among other benefits. Meanwhile, the CMOS IC industry is also embracing new device architectures, namely, the variants of multi-gate transistors, such as FinFETs, Tri-Gate FETs, and ET/UTBB SOI FETs, to overcome scaling limitations of bulk transistors. New SPICE models have been, or are being established as an industry standard for this new class of devices.

While the academic research has been bearing the burden of developing and improving the CMOS model framework, the industry has focused on model extraction methodologies and work flow for automation and efficiency, as well as on physical effects that used to be second-order but have risen to the par of primary MOSFET physics in their impact and importance. For example, parasitics de-embedding and modeling is no longer a task exclusive for RF applications. It has become an integral component of device models for digital ICs. As a special case, modeling of layout dependent effects (LDE), which are a byproduct of mobility enhancement techniques through strain engineering, requires well beyond model equations and parameter extraction to include extensive test structure design and laborious measurement data analysis. Process variation and mismatch modeling has come of age in device model libraries, although new challenges may lie ahead such as spatial and cross-device correlation. While the corner methodology remains the dominant approach in design flows, it is a pressing and growing challenge to define and develop meaningful device corner libraries, especially for analog designs with numerous and often conflicting figures of merit. It is worth noting that the need and necessity for statistical and corner models extend, in addition to DC and AC behavior, to other characteristics as well, such flicker noise and aging effects. Recognizing that design-level validation is the ultimate verdict on SPICE models’ quality, the industry is witnessing increased and direct use of benchmark circuits such as the SRAM bit cell and ring oscillators for model parameter extraction. As the complexity of ICs keeps increasing to incorporate ever expanding functionalities, many of the modeling challenges for CMOS FETs become applicable for integrated passives.

In parallel to being driven aggressively by digital ICs, CMOS technology has been extended to serve a large number of other applications, which have become collectively known as More-than-Moore (MtM) technology. On the one hand, the MtM technology enabled applications are required to interact with our analog-centric world, such as sensors, actuators, RF transceivers, power management, and high-voltage drivers. On the other hand, it becomes feasible by leveraging well amortized equipment and maturity of a CMOS manufacturing line to deliver cost-effective solutions either to displace traditionally non-CMOS technologies or create new commercially viable mass markets. For these applications, device modeling needs to address distinctly different technical issues, such as breakdown voltage, self-heating, large-signal behavior etc. to deliver application-specific SPICE models.

Although there may be different business models to design and manufacture ICs, whether at an integrated device manufacturer (IDM) or with the foundry-fabless model, concurrent design has become commonplace to shorten the time to market. It has had profound implications on device model extraction practice. Characteristic to supporting concurrent designs, device models need to be extracted well before a manufacturing technology is developed or made stably yielding, and as a result, incur regular refinements to reflect technology changes as well as design specs updates. In this case, a device model is extracted not based on measurement data, either IV/CV sweeps or spot measurement, but based on projected device characteristics, known as targets, and such practice is referred to as target-based or speculative model extraction. In an effort to provide more meaningful guidelines for target-based models, the number of device targets has exploded from the minimum of drive current and threshold voltage in the past to a plethora of characteristics and their derivatives across device geometries and biasing conditions. Aside from being driven by concurrent designs, the need for target-based modeling also results from gaining competitive advantage by design houses. First, being able to modify and customize foundry-provided SPICE libraries to device targets derived from internal design specs significantly speeds up the model/design iterations. Second, although foundry models have evolved significantly and achieved impressive quality overall, they may still fall short for certain specific applications not foreseen or characterized during extraction. Therefore, being able to customize foundry libraries in-house to remove model deficiencies provides competitive advantage and is deemed essential for leading design houses.

Keysight's Model Builder Program (MBP) has been developed to meet the challenges in silicon device model extraction. It provides superior efficiency through a rich set of GUI-based features, automatic extraction routines, and flexibility for custom flow development. It also provides turnkey solutions for all the major modeling tasks beyond core model extraction. MBP offers unique solutions for design houses to support the concurrent design methodology. To learn more how MBP may help with various SPICE modeling activities in foundries, at IDMs and design houses, refer to Model Builder Program (MBP) -- Silicon-Focused Device Modeling Software.