Physical Layer Validation Challenges of Characterizing 100/200 Gbps/lane Designs

Demos

This session will be a practical discussion of IEEE 802.3ck (100Gbps/lane) physical layer conformal testing for both Tx and Rx. 100G silicon is emerging from the early specifications and a world of simulation. This track will help bridge the gap between simulation and physical layer evaluation of SERDES design and conformance testing.