Investigating Load Pull and DC Simulations of a Cree FET
Application Notes
Introduction
This application note describes a workspace 1 that features several load pull and DC I-V simulations of a Cree Field-Effect Transistor (FET). The workspace may be used to see what performance (e.g., output power, gain and power-added efficiency (PAE)) could be obtained, and what source and load impedances should be used to attain a desired level of performance (or make trade-offs). Using the schematics and data displays, you will be able to determine things like:
- How much output power can be attained? At what level of gain or gain compression?
- At a desired output power, what gain, gain compression, power-added efficiency, bias current, adjacent channel power ratio (ACPR), and error vector magnitude (EVM) can be attained? At what source and load impedances?
- How sensitive is the performance to the load impedance?
- How do the optimal load impedances vary with frequency or bias, or some other parameter like parasitic source inductance?
- How does performance depend on the source impedance?
- How does performance depend on the 2nd and 3rd harmonic impedances at the load or source?
- What trade-offs can be made between output power and power-added efficiency?