Data Sheets
Overview
The M5400DMOA allows quick and easy access to targeted quantum signal processing FPGA IP blocks used within PathWave FPGA to complete an entire demodulation IQ path with customizable configurations that include real-time sequenced triggering, digital down-sampling and custom filtering, qubit state detection and multi tone capable IQ data memory management all designed and optimized to be used with the M3102A real time control hardware platform.
The M5400DMOA software package
This licensed software package for the quantum library includes a quantum M5400DMOA programming API that directly interacts the SD1 3.X driver communication, KS2201A PathWave Test Sync Executive and Quantum FPGA IP library for a user friendly programming environment that can quickly be used for qubit control and readout applications.
Using the fully integrated software and FPGA Gateware package allows for simplifying your configuration and provides massive savings of development time to integrate and expand to multi qubit systems including multi-chassis configurations for scaling system configurations.
Features
The Quantum FPGA IP provides ultra-light weight and scalable components that have a small FPGA footprint that allows for frequency division multiplexing capable for multi qubit readout. The convenient quantum FPGA IP provides the ability to phase lock to the M320xA AWG with no external references required. Using precise real-time control through PathWave Test Sync Executive technology known as HVI, hardware virtual instrument, allows for deterministic triggering that is synchronized with the M320XA PXIe instrument AWG.
• DDC - Digital downconverter with custom programmable dual LO that is phase adjustable to rotate and accommodate IQ constellations.
• Digital Downsampler with customizable integrating rectangular or customer filter windows including decimation.
• Qubit Decoder for qubit state discrimination for active |1> or ground state |0> through amplitude and phase detection using a single threshold detection technique from a single IQ point readout pulse result.
• Data Wrappers that handle data management of IQ and state data for up to 16 qubits on a single M3102A PXIe module.
Table 1-1: Technical Performance Specifications (IP Components)
IP Component |
|
|
Nominal Characteristics |
|
||
|
Parameter |
Min. |
Typ. |
Max. |
Units |
Comments |
DDC |
|
|
|
|
||
|
Frequency |
0 |
|
200 |
MHz |
5.68 µHz resolution; 45 bits |
Phase |
-180 |
|
180 |
degree |
21.5 µdegree resolution; 24 bits |
|
IP Component |
|
|
Nominal Characteristics |
|||
|
Parameter |
Min. |
Typ. |
Max. |
Units |
Comments |
DownsamplerX5N |
|
|
|
|
|
|
|
Filter Type |
rectangular |
|
custom |
window |
rectangular (average) custom (time-based coefficients) |
Rectangular Length |
10 |
|
65535 |
samples |
20 ns to 1.31 ms; 5 ns increments |
|
Custom Length |
10 |
|
10240 |
samples |
20 ns to 20 µs; 5 ns increments |
|
Latency |
|
10 |
|
ns |
after readout pulse |
|
Qubit Decoder |
|
|
|
|||
|
Threshold |
-1.5 |
|
1.5 |
Volts |
DC threshold applied after demodulation filter window |
Latency |
|
10 |
|
ns |
after downsampler |
|
DataWrapperXN |
|
|
configurations support IFIQ on single channel or IQ baseband inputs across two channel inputs |
|||
|
Cycles |
1 |
|
3x1e6 |
cycle |
Supports up to 3M triggers of IQ and state data samples per qubit |
Custom Filter |
1 |
|
16 |
qubits/module |
IQ IFIQ configuration across 4 channels. See utilization table below |
|
Rectangular |
1 |
|
8 |
qubits/module |
IFIQ configuration across 2 channels. See utilization table below |
|
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