P5573A PCI Express Protocol Exerciser for PCIe 6.0

Introduction

P5573A PCIe 6.0 Protocol Exerciser allows test engineers to emulate both PCIe root complex and endpoint devices when validating PCIe designs. The exerciser supports traffic generation from 2.5 GT/s through 64 GT/s and lane widths from x1 to x16. The tool includes over 100 built-in LTSSM test cases, error insertion capability at the TLP and DLLP layer, and an included protocol checker.

Product Overview

The Keysight P5573A PCIe 6.0 Protocol Exerciser provides test and validation engineers a powerful tool for vetting and debugging their PCIe designs. The P5573A uses an integrated, single add-in-card design which greatly simplifies the connection and setup of the tool while offering greatly improved signal integrity compared to other architectures. This enables test and validation engineers to focus their time and energy on designing and automating unique test cases for their products, rather than wasting time dealing with an overly complex test setup with poor signal integrity.

The foundation of the P5573A is the improved signal integrity provided through the integrated design of the Exerciser card which provides a solid, trustworthy test platform. This compact design allows Keysight engineers great versatility in ensuring that the P5573A would have signal integrity characteristics that could be configurable enough to be tuned for many different test environments, while also offering quick link up capability for test cases that focus on higher layer protocol debugging.

The P5573A Exerciser supports PCIe speeds from 2.5 GT/s up to 64 GT/s and Lane widths from x4, x8 and x16 along with the following features:

• Follows all PCIe 6.0 electrical specifications.

• Automated link training to 64GT/s

• Ability to initiate Higher and Lower Speed Changes between 2.5GT/s to max supported speed.

• PCIe 6.0 link training bypass supported

• Traffic generation directly from GUI or from automated user generated scripts.

• Lane Reversal and polarity detection

• Scalable flow control supported

• Control of the Link Training and Status State Machine (LTSSM) operation

• Lane and Speed Negotiations from 2.5 GT/s to 64 GT/s.

• Real Time Equalization process

• Transaction Layer Generation (Memory Read/Write, IO Request, Config Request)

• Error Insertion via NAK, Completion Error, DLLP Errors

• Emulate either upstream (Root Complex) or downstream (Endpoint) ports

Combined Exerciser and Analyzer Software

Both the Keysight P5573A PCIe 6.0 Protocol Exerciser and its companion tool, the P5570A PCIe 6.0 Analyzer, are supported by a single combined software interface, offering the user easy access to all of the powerful capabilities of both tools. Through a simple, tab based interface, the user can configure the Exerciser and Analyzer side by side with just a few clicks. The Exerciser GUI provides deep functionality for configuring Traffic Setup, while also providing improved data exchange with the analyzer.

Use Case: Root Complex Emulation for Testing Endpoints

The Keysight P5573A can be configured to emulate a PCIe 6.0 root complex with its own link, equalization, and power management parameters.

When emulating a root complex, the P5573A cards can connect to a PCIe slot on the P5563B test backplane board with an endpoint (DUT) sitting in another PCIe slot. The exerciser then provides downstream stimulus to the DUT as a root complex just as a regular Host System would. The exerciser then can check the data received from the DUT for errors. This common configuration is simple to setup and easy for the end user to operate and troubleshoot.

Use Case: PCIe End Point Emulation for Testing Root Complex

When emulating an end point the PCIe exerciser card can be plugged into any PCIe slot on a system motherboard, similar to how any other PCIe add-in-card device, such as a NIC, Graphics Card, or SSD, would be plugged in.

The P5573A PCIe 6.0 Protocol Analyzer can also be added to the above configuration to decode and analyze the traffic between the system motherboard and the emulated end point.

Ready to Go Protocol Test Features

The P5573A is designed to be easy to setup, connect, and be quickly configured to bring up the PCIe link and check basic LTSSM and protocol functionality. To support this the P5573A has many features included that allow for quick validation of fundamental PCIe features.