Testing DDR5 Input Clock Jitter
Application Notes
Clock jitter refers to the deviations in timing from a clock’s ideal signal transitions. These variations are typically caused by factors such as thermal noise, fluctuations in power supply, load conditions, intrinsic device noise, and electromagnetic interference from nearby circuits. Since all DRAM command and address inputs are synchronized to the clock, the jitter must remain within the limits defined by the Joint Electron Device Engineering Council (JEDEC) to ensure reliable operation.