Webinar
At next-generation data rates, passing compliance is only part of the challenge.
In the final technical session of our three-part AI Scale-Up Insider Series, see practical demonstrations of transmitter and receiver validation, signal analysis, margin evaluation, and automated debug across PCI Express® 7.0, DDR6, IEEE 802.3dj, Ultra Accelerator Link (UALink), and related interfaces.
Learn how modern measurement and validation workflows can help engineers identify root causes faster, increase validation confidence, and reduce debug time.
PCIe® and the PCI Express® are US registered trademarks and/or service marks of PCI-SIG.
Development and validation engineers, signal integrity engineers, data center architects, and technical leaders working in AI infrastructure, compute I/O, memory, fabric, signal integrity, and system validation. This session is especially relevant to those responsible for characterizing, validating, or debugging the high-speed components, interfaces, and interconnects that enable AI system scale-up.
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