IxVerify

Here's the page we think you wanted. See search results instead:

Chat Live

Welcome

You are signed as:

My Profile
Logout

Please Confirm

Confirm your country to access relevant pricing, special offers, events, and contact information.

What are you looking for?

I'm looking for support MXG Signal Generator UXA Signal Analyzer PXA Signal Analyzer Find a solution Get technical support Take a class Find us at events Premium used equipment KeysightCare Buy online

No product matches found - System Exception

Highlights

Test Router, Switch, SmartNIC or Automotive Application-Specific Integrated Circuit (ASIC) and System-on-a-Chip (SoC) designs in emulation.
Integrate with top three EDA emulators to accurately validate protocols and features of the chip design and avoid costly re-spins.
Inject captured or synthetic traffic over MAC, PCS or PMA Ethernet transactors with line speeds up to 1.6Tb to test design robustness.
Re-use test configurations and scripts between pre-silicon and post-silicon test phases to accelerate time to market.

Ensure zero packet loss and accurate synchronization between virtual environment and the emulation system.
Use elastic virtual test solution with support for globally distributed users.
Access statistics in emulation time.
Support automation with REST, Python, TCL, Perl, and Ruby.

Problem: Network Chip Design Verification Happens Too Late in the Development Cycle

Increased use of end-user streaming applications or cloud computing require low-latency, high-throughput, and secure traffic that are pushing the boundaries of network capacity. This demand drives the market for ultra-high-speed Switches, Routers or SmartNICs, powered by state-of-the-art ASICs / SoCs. Not shifting left the test cycle or using imprecise pre-silicon test tools may result in costly chip re-spins or low performing hardware.

Solution: Verify the largest Networking chip designs with dynamically shaped traffic

IxVerify provides 450+ predefined packet templates for testing Ethernet and networking protocols and can generate high volumes of clear or MACsec encrypted traffic while measuring per-packet latencies with nanosecond accuracy. Its unique ability to push traffic through hundreds of virtual interfaces at the same time ensures a robust and close to real-life testing of the emulated Switch, Router or SmartNIC chipset design. Protocol impairments enable negative testing which adds another layer of validation of the design under test.

IxVerify deployment in an emulation-based design verification environment.

Problem: Testing TSN capable chipset designs in pre-silicon is inaccurate without the right tools and timing synchronization

Automotive chipsets require accurate time synchronization and TSN feature support to ensure specification compliance and smooth interoperability. Without the right infrastructure and methodology, TSN features cannot be tested in pre-silicon phase which is jeopardizing the chipset post-tape out acceptance.

Solution: Test Automotive or Industrial TSN emulated designs in a time-synchronized environment

IxVerify’s patented IP developed to interconnect with the EDA emulators ensures lossless traffic, accurate timing synchronization and statistics in emulation time, which are critical to testing TSN features in pre-silicon. Using the same test methodologies in pre- and post-silicon testing enables valid result comparison and precise ASIC benchmarking in all its phases.

Full TSN testing support on both Industrial and Automotive latest specifications enable design feature testing of IEEE802.1AS, IEEE802.1Qbu / IEEE802.3br, IEEE802.1CB, IEEE802.1Qav, IEEE802.1Qbv, IEEE802.1Qci, IEEE 172-2016 or IEEE 1588 v1 / v2 specs with sub nano-second accuracy.