Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools

Key takeaways:

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and maintaining good reputations throughout their lifetimes.

Unfortunately, many SoC teams attempt to use existing tools like Git for these essential tasks, even though they are unsuitable and inconvenient in the long term.

In this article, understand the need for, and essential features of, semiconductor IP catalogs and their critical role in IP management and tracking. Also, discover how they facilitate semiconductor IP reuse.

What is semiconductor design IP management?

Design IP management involves the systematic search, details lookup, suitability analysis, usage tracking, dependency tracking, and change handling of all the semiconductor IP cores used or created during the product lifecycle of an integrated circuit (IC) or SoC.

What are IP cores?

IP cores are the building blocks of an SoC or IC design. Each IP core is a standalone semiconductor module that encapsulates a set of functionalities of the SoC or IC.

Some common examples of general-purpose IP cores include:

Some examples of IP cores for application-specific ICs (ASIC) include:

The importance of IP cores in design IP management

A diagram of a software process Description automatically generated

Fig 1. IP cores in traditional SoC design

In traditional SoC designs, IP cores are used as follows:

  1. The constituent IP cores are integrated through a communication bus or a network-on-chip.
  2. This integration is described by a single register transfer level (RTL) design. SoC engineers prefer soft IP cores for their flexibility as they are described by high-level RTL designs that can be modified and synthesized to suit the SoC's process technology, power, and performance targets. In contrast, hard IP cores are only available as unmodifiable, process-specific, physical layout files, which makes them much harder to integrate into an SoC.
  3. The RTL design then undergoes a logic synthesis step to derive a netlist.
  4. This netlist is optimized for the chosen process technology while satisfying timing, area, and power constraints.

This implies that all the selected IP cores must be compatible with that process technology from the start. The original IP cores are modified and adapted for the selected process technology in the synthesis step by the system integrator company. All this adaptation followed by verification can be quite time-consuming and inefficient for fast-moving industries like consumer electronics.

A diagram of a computer chip Description automatically generated

Fig 2. IP cores in chiplet SoC design

To address such shortcomings, the semiconductor industry has been evolving toward usingchiplets forSoC designs. The key difference of this approach is that the chiplets of an SoC can follow different process technologies. So the chiplets can be independently designed by domain-specialist IP vendors using any process technology and integrated faster without an RTL step as long as it conforms to one of the chiplet communication standards (like the chip-on-wafer-on-substrate interface or the universal chiplet interconnect express).

What does all this mean for design IP management? These processes place the following requirements on an SoC integrator's IP management methodology:

Challenges in design IP management and reuse

Some key challenges of IP management are outlined below:

Apart from the above general challenges of IP management, effective semiconductor IP reuse involves some additional challenges:

What is a semiconductor IP catalog, and how does it improve design IP management?

An IP catalog is a centralized digital repository with detailed information about all the semiconductor IP blocks being used and available for use in an organization. It contains comprehensive details about every internal and third-party IP block:

For IP development of new designs by an organization for internal use or external partners, the IP catalog can also store proprietary information like:

The semiconductor IP catalog is at the heart of efficient semiconductor intellectual property management. It helps to achieve several positive outcomes like:

From the organization's point of view, the semiconductor IP catalog breaks down silos by offering centralized repositories. This in turn promotes more collaboration among design engineers across teams and sites since they're all able to access the same information about a design.

Lastly, since the semiconductor IP catalog manages information for the entire lifecycle of an IC or SoC, it serves as the organizational memory about the IC design. Its information persists even as teams and roles change over time. If design bugs are found decades later, the engineers at the time can dive into the design's history recorded in the catalog. They can trace the technical and business decisions that resulted in the bug and design suitable workarounds.

Why traditional and retrofit approaches to IP management fail

file sizes for MMIC, Analog, PDK, digital design

Fig 3. Storage capacity required for design data

Many semiconductor companies have attempted to retrofit existing software systems to implement semiconductor IP catalogs. Such software systems include:

Another traditional approach, followed by some companies, is to rapidly develop rudimentary in-house tools specifically for IP management.

However, all these approaches have many shortcomings:

  1. Poor cataloging and search capabilities: These tools were not built for scale. They are incapable of efficiently cataloging and searching an organization's entire IP portfolio, which may be in the thousands.
  2. Missing hierarchy and dependency management: Version control tools treat each code file as an independent unit without any dependency tracking between files. In contrast, chip design involves a multi-level dependency hierarchy of IP cores. If a heavily reused IP core changes, those changes must bubble up through all the cores above it in the hierarchy, triggering regression tests and other verifications for each affected core. Additionally, the changes must bubble up to all the projects that depend on that core at any level. Such change propagation is just not built into tools like Git.
  3. Lack of design tool integration: Existing and in-house tools often lack integration with the EDA and other design tools that the design engineers are using. This leads to workflow inefficiencies and design inconsistencies.
  4. Inability to handle large files: Typical data capacity requirements for chip design workflows range from hundreds of gigabytes to a few terabytes, as shown in the illustration above. Git is just not designed to efficiently store such large files.
  5. Unsuitability for binary design files: Another limitation of tools like Git is their clumsiness with binary formats. Most chip design data consists of binary format files. Understanding and visualizing any changes to them is essential, but Git isn't capable of that. Minor changes in a binary file can't be incrementally updated, forcing the entire file to be re-uploaded.
  6. Inconsistent versions: Although Git is a distributed version control system, its sync workflows are inconvenient for users and inefficient with the large binary files prevalent in chip design. So different teams may end up working on different versions of the chip design files, resulting in inconsistencies and compatibility errors at tape out.
  7. Problems with IP security: These tools are not suitable for access control that is both fine-grained and domain-aware. For example, you may want to ensure that a layout engineer doesn’t change a schematic and prevent contractors from accessing sensitive design libraries. This kind of nuanced access control isn't easy with such tools.
  8. Unawareness about legal conditions: These tools don't facilitate compliance with licensing and usage restrictions.

Why a purpose-built semiconductor IP catalog is the right solution

Purpose-built solutions for chip design data and IP management that are architected from scratch specifically for chip design use cases are essential for your SoC engineers. They can scale up to enterprise-wide usage and enhance your return on investment.

Their benefits include:

  1. Accurate searching and matching: IP core search and match helps engineers locate and compare all the IP available across the enterprise — whether third-party or internal — throughout the engineering lifecycle. Though different business units may work like knowledge silos, the systematic publishing of all IP cores to a central catalog with standardized metadata enables engineers across business units to be aware of each others' IP designs and reuse them.
  2. Hierarchy awareness: These tools automatically identify IP dependencies and track IP usage across an enterprise. Whenever an IP core changes, they trigger automated actions for all affected cores. They are aware of chip design complexity.
  3. Native integration with EDA tools: As soon as a change is done from an EDA tool, those changes are automatically and efficiently propagated throughout the enterprise.
  4. Large binary file support: These tools can render file changes as visual changes in design diagrams. They enable engineers to access design data without downloading the entire set of large binary files to local workstations, which would be prohibitively slow and blow up network usage costs if any. Another benefit is their ability to upload incremental changes quickly without re-submitting entire files.
  5. Centralized repository for consistent views: By maintaining all the data centrally and downloading them to workstations efficiently, all users across the enterprise anywhere in the world see the same file data at all times.
  6. Secured IP: Purpose-built tools implement robust data security and access controls.
  7. Awareness of licensing and usage restrictions: These tools provide built-in support for storing and analyzing licensing terms and other legal requirements.

Case study: How Allegro reduced their design time with Keysight IP management solutions

Allegro MicroSystems is a leading designer of automotive, industrial, and power management ICs. Before 2005, their IP management workflows faced challenges like:

By adopting Keysight HUB and SOS, all business units across Allegro could systematically publish their IP designs to the central IP catalog with standardized metadata. Other teams were able to easily search and retrieve IP metadata. Traceability and compliance improved due to HUB's ability to track IP use across projects and business units.

Keysight HUB and SOS enable the enterprise-level tracking of over 200 IPs across 150 projects. Nearly 55% of Allegro’s IPs today are derived and modified from proven template IPs, enabling as much as 45%-50% reduction in design time, shorter engineering life cycles, and faster time-to-market.

Use Keysight's powerful solutions for IP and design data management

A screenshot of a computer Description automatically generated Fig 4. Compare IP cores in Keysight HUB

Keysight HUB is our powerful solution for semiconductor IP management. It provides all the benefits of the purpose-built solutions explained above. More specifically:

Keysight SOS, Keysight Design Data Management, Cliosoft, SOS7

Fig 5. Keysight SOS for hierarchical IC design data management

Keysight SOS is our feature-rich high-performance system for design data management. Together with HUB, it enables design teams to efficiently store and sync design data, track changes, automate traceability reporting, and collaborate with other teams in real time to solve any design problems.

Want help or have questions?

Contact us