What is a Chiplet, and Why Should You Care?
Chiplets are a new way to build system-on-chips (SoCs) that can improve yields and reduce costs by more than 45%. It partitions the chip into discrete elements and connects them with a standardized interface, allowing designers to meet performance, efficiency, power, size, and cost challenges in the 5/6G, AI, and VR era.
Unlike monolithic SoCs, chiplets enable an open ecosystem of modular components that can be reused and customized. But what exactly is a chiplet and what are the advantages of using it?
What is a Chiplet?
A chiplet is a small, modular chip that performs a specific function very well. For example, a chiplet can be a processor core, a memory block, an I/O driver, or a signal processing unit. Chiplets are designed to be used in a chiplet-based architecture, in which multiple chiplets are connected through a standardized high-speed digital interface to form a complete system-on-chip (SoC).
Figure 1: Simplified Chiplet Standard Package View
This way, you can create complex and powerful SoCs by mixing and matching different functions and technologies to create a customized system without having to fit all the components onto a single monolithic chip.
What are the Benefits of Chiplets?
There are several key benefits of adopting chiplet technology:
- Optimized Performance and Power: Chiplets can be optimized for their specific functions and technologies, improving the SoC's performance and power efficiency. Chiplets can also be placed closer together, reducing the interconnects' latency and power consumption.
- Lower Manufacturing Cost: Chiplets can be fabricated using different process nodes and foundries, which reduces the cost and risk of producing large, complex chips. Chiplets can also be reused across different SoCs, which increases the return on investment and reduces the time-to-market.
- Higher Flexibility and Scalability: Chiplets can be easily added or removed to adjust the functionality and performance of the SoC. Chiplets can also be updated or replaced without affecting the rest of the SoC, which enables faster innovation and adaptation to changing market demands.
Figure 2: Chiplet vs. monolithic die approach performance and cost comparison.
Challenges of Chiplet Design
Although the chiplet’s modular approach increases yield, the functional blocks are now on different dies, often from different vendors. Designers cannot probe inside each functional chiplet in an SoC, which increases design complexity. Advanced simulation and adopting modern EDA solutions supporting the chiplet workflow become critical activities to address this.
Another major challenge of chiplet design is communication between the chiplets, die-to-die (D2D) communication. A robust and standardized D2D communication is crucial in establishing the reliability and interoperability of chiplet-based designs. UCIe is an open standard rising to standardize D2D communication and improve chiplet designs reliability and interoperability.
How Chiplets are Changing the SoC Design Workflow
Chiplets are revolutionizing the SoC design by enabling a new level of heterogeneity and modularity. Chiplets allow designers to leverage the best of different technologies and domains, such as logic, memory, analog, RF, and photonics, to create high-performance and power-efficient electronics.
It enables a new paradigm of design automation, in which chiplets can be selected, assembled, and optimized to create highly customizable SoC that meets specific design objectives and constraints.
As a result, the design workflow is becoming highly iterative, and the traditional design center’s approach, which is serialized, is becoming very time-consuming and inefficient.
Designers will need agility and cross-function collaboration to meet technology and market demands. This includes better concept, design, and simulation tools that reduce time-to-insight, eliminate unnecessary prototype spins, and remove knowledge silos.
And that’s where Keysight’s Modern Design Center approach comes in. It uses tightly integrated software to enable reproducible and scalable automation, allowing designers to focus on where it matters the most: assessing and validating electronic designs more confidently and collaboratively.
Figure 3: Examples of how integrated software accelerates SoC Design.
For example, Keysight EDA Chiplet PHY Designer, part of the Keysight EDA Advanced Design System (ADS), is the first in the industry to help chiplet designers model and analyze the signal integrity from one die to another. It is UCIe standard-focused, and it provides designers with a higher-level abstraction layer to explore a broader range of design scenarios simulating UCIe, measuring VTF, and analyzing forward clocking without spending time with manual and repetitive tasks.
Figure 4: Keysight EDA Chiplet PHY Designer end-to-end design workflow.
As shown in Figure 4, it uses graphical representations to help designers configure the transmitter, chiplet interconnect, and receiver. This intuitive user workflow reduces the time spent learning to use the software.
It includes a PHY designer and simulator, a via designer, a controlled impedance line designer (CILD), and an EM designer that enables the creation and import of parameterized 3D components into ADS.
Figure 5: Chipley PHY Designer Workspace.
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Conclusion
Chiplets are a promising alternative to monolithic SoCs that offer lower costs, higher performance, and greater flexibility. Chiplets are also a key enabler of heterogeneous and modular SoC design, which can accelerate innovation and adaptation in the electronic industry. Keysight Modern Design Center enables reproducible and scalable automation so designers can pathfind for next-generation technologies more confidently.
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