Why Semiconductor Design Teams Can’t Afford Disconnected Workflows

Semiconductor design teams are under pressure to innovate faster, yet many still struggle with disconnected workflows and siloed design data. When critical IP is spread across tools, regions, and teams, productivity suffers, collaboration breaks down, and AI initiatives stall before they start. To compete, leaders need more than incremental fixes — they need a global design platform that unifies data, enables true workflow integration, and makes their organizations AI-ready.

Try Keysight Data Management Software (SOS)

Key takeaways:

• U.S. chip companies face a challenging business environment due to a severe shortage of designers, growing fabrication costs, and uncertain government policies.
• By optimizing their day-to-day engineering tasks, chip companies can effectively address many of their business challenges.
• Global design platforms, like Keysight SOS for semiconductor design data management, help in streamlining day-to-day chip design tasks to maximize productivity.

The semiconductor sector, especially in the U.S., faces several headwinds. Customers are demanding features that require advanced semiconductor designs. The costs of designing, fabrication, quality control, and regulatory compliance keep going up. Meanwhile, market competitiveness forces designers to do a lot more in less time.

In this challenging business environment, global design platforms, like Keysight SOS for design data management, enable chip manufacturers and semiconductor foundries to streamline their workflows and maximize organizational productivity. In this blog, find out what problems are solved by global design platforms for next-generation chips.

Why there’s a need for global centers of excellence in chip design

Figure 1. Semiconductor center of excellence

Let's look at why semiconductor businesses must establish global centers of excellence (CoEs) for chip design and streamline their collaboration. Note: Chip design here refers to the end-to-end steps required for the design and fabrication of an integrated circuit (IC), central processing unit (CPU), system-on-chip (SoC), intellectual property (IP) core, or chiplet.

By 2013, McKinsey had already noticed that the increasing complexity ofchip design was causing engineering productivity to drop and costs to balloon. This trend has worsened over the past decade.

Following the 2020 pandemic, the world saw a global chip shortage, first due to disrupted supply chains and later due to the high pent-up demand.

Today, in 2025, the U.S. semiconductor industry faces a projected shortageof 23,000 skilledchip designers by 2030. Meanwhile, the cost of designing a new chip has seen an 18x increase — from $30 million in 2006 to $540 million in 2020.

In this difficult business environment, establishing global CoEs is a wise initiative that enables chip companies to alleviate some of these problems and facilitate different business goals as outlined below.

Attract much-needed engineering talent

A reputed CoE can attract an experienced, skilled semiconductor workforce in all areas of chip design, like wafer engineering, lithography, photonics, and more. They would have already gained critical skills by working in semiconductor research labs, semiconductor design companies (fab or fabless), or silicon foundries.

Enabling engineering talent around the world is smart engineering and the future of competitive innovation. At Keysight, we see first-hand how global design teams collaborate to solve complex validation and simulation challenges — from RF to photonics to power systems.

Stick to design schedules

The fast pace of innovation and rigorous competition in crowded industries like smartphones requires fast turnaround times. Multiple CoEs spread out globally across different time zones means the design, verification, prototyping, tape-out, and refinement spins can be kept tight at all times.

Maintain business flexibility

Multiple CoEs enable flexibility and redundancy at the business level. If a CoE has to stop work due to natural disasters or other disruptions, another CoE can step in to take over the work.

Speed up team communications

By encouraging extensive collaboration and communication between CoEs, institutional knowledge and expertise can organically spread throughout the company workforce and streamline each CoE's local workflows with the latest findings.

What are the obstacles to efficient multi-site collaboration on chip designs?

Some of the more egregious pain points that hamper multi-site chip design collaboration between CoEs are described below.

Storage management issues

Figure 2. Chip design data volumes

The first major technical challenge is the sheer volume of chip design data. Each SoC design and variant produces about 1-2 terabytes of files.

So much data must be downloaded to hundreds of engineers' workstations and their changes must be synced in real time. Doing that while keeping the user experience fast, snappy, and productive imposes enormous demands on the performance of the storage, network, and enterprise version control systems.

Version control challenges

Common version control systems (VCS), whether open-source like Git or closed-source ones, are not suited forchip design. Their version control engines are not optimized for the chip design ecosystem. Problems like this are common:

• Performance issues: Since some files take up megabytes or even gigabytes, the storage and network infrastructure can become bottlenecks for rapid fine-grained version control operations like checking out, committing, and comparing changes.
• Clumsy integration with design tools: Common VCS tools are not seamlessly integrated with the electronic design automation (EDA) tools and workflows that chip designers and engineers use. As a result, day-to-day work can be frustrating and productivity can go down.
• No concurrent editing: Common VCS tools are designed for text-format code files whose multiple overlapping edits are easy to merge. But chip schematics and layouts are more like images. Common VCS tools don't have the domain knowledge and geometrical awareness needed for concurrent editing of such image-like chip design data.
• Poor binary file handling: Common VCS tools don't enable the visualization, comparison, and merging of large binary files that are prevalent in the semiconductor ecosystem.

IP reuse problems

Pre-designed, pre-verified IP cores significantly accelerate the semiconductor engineering process. However, finding the right IP core that satisfies different functional, performance, security, and cost requirements can be challenging because a single source of truth for such information is often missing.

Secondly, finding and evaluating all their simulation and test results to assess suitability is a laborious process.

Lastly, discovering their security and regulatory compliance requirements can be challenging.

Knowledge silos

The culture of secretiveness in chip design companies helps to protect valuable intellectual property but can also lead to siloed knowledge. A team may have already developed a deep understanding of some IP core, but the siloing can prevent their knowledge from organically reaching other project teams, robbing the business of an opportunity to increase its overall productivity.

Documentation and traceability challenges

Chip design involves plenty of internal and partner documents like:

• datasheets
• interface specifications
• performance specifications
• simulation guides
• physical synthesis and layout guidelines
• release notes
• compliance reports
• licensing and non-disclosure agreements

Each of these may have multiple versions. Finding and retrieving the exact document and version that a designer needs requires highly capable document management and information retrieval features.

Inefficient manual processes

Many companies continue with inefficient manual workflows for design change reviews, approvals, IP discovery, collaboration, procurement, and more.

What are some industry-specific design challenges?

Besides the general challenges of semiconductor design, every critical downstream industry that involves several global chip design teams faces unique additional challenges as outlined below.

Automotive

Automotive industry chip design involves additional challenges like these:

• Long operational lifetimes: The average lifespan of cars in the U.S. is about 12 years. All the chips inside must also operate for these durations, possibly under harsh road and weather conditions.
• Stringent safety culture: The automotive safety culture remains very stringent and accountable. Even older models are regularly checked for faults and recalled. This requires chip companies to build up long-term institutional memories by systematically retaining past knowledge of their designs and decisions.
• End-to-end traceability: The International Organization for Standardization 26262functional safety specifications require automotive chips to maintain end-to-end traceability between requirements and verification stages.

Artificial intelligence (AI)

The generative AI and large language models revolution is being powered by data center accelerator chips based on cutting-edge advancements like:

• tensorcores
• single-instruction-multiple-threads stream processor architectures
• multi-die integration ofchiplets
• universalchiplet interconnect express
• high-bandwidth memory

These advanced chip designs used by devices like graphics processing unit (GPU) chips are fundamentally different from the designs of general-purpose microprocessors. However, both types of chips integrate a large number of specialized subsystems.

Each of these subsystems is complex by itself, requiring specialist knowledge through a semiconductor center of excellence or partnership with a third-party IP vendor. Keeping so many specialist stakeholders on the same page at all times is technically and organizationally challenging.

5G/6G telecommunications

The chips used in 5G/6G communications are mixed-signal devices with both radio frequency IC and high-speed digital IC components. The design data and IP management for such mixed-signal designs involve challenges like:

• Common global configuration management approaches can't easily manage mixed-signal designs.
• Each vendor tends to provide its specialized design tools. As a result, design workflows can get incredibly complex with several tools from multiple vendors.
• Version control is usually not integrated by these vendor tools.
• Poor practices — like copying designs between scratch and master libraries and disabled access controls — are common. Faced with the inherent complexity of analog IC design and often incompatible tools, designers just want to get things done. But such practices can easily introduce design errors and cause permanent loss of knowledge.

Keysight SOS — a powerful global design platform for semiconductor challenges

The solution to all these general and industry-specific problems is a global design platform that is built from the ground up to facilitate world-class global design collaboration and semiconductor engineering lifecycle management.

Keysight's global design platform, SOS, is a tailor-made solution for semiconductor design data management. It's part of a comprehensive design data management and IP management solution for the global semiconductor industry.

In the following sections, we explore the features and benefits of Keysight SOS and explain how it addresses the collaboration challenges of semiconductor design.

Comprehensive design data management

Figure 3. Keysight SOS

The heart of Keysight SOS is a centralized repository to store all the design data of a chip in one place. That includes all the:

• requirements
• specifications
• intermediate design files
• simulation models
• tapeout files
• technical documents
• embedded software code
• test data and code
• legal documents
• regulatory reports

Data from internal teams as well as third-party vendors can be stored in the same place.

This extensive data is neatly arranged under the relevant subsystem and component for convenient browsing and management.

Granular access control and permissions per user, item, and action enforce strict need-to-know and data security without harming the user experience and usability.

Streamlined multi-site collaboration

Figure 4. Keysight SOS architecture

Keysight SOS acts as the single source of truth for a chip design. Every team anywhere in the world sees the same files and versions.

Highly optimized downloads, storage, and network transfers

Figure 5. Git vs. SOS cloning

Keysight SOS downloads a design project's files to an engineer's workstation very efficiently. Even if the total storage size is a couple of terabytes, downloading is an extremely fast operation that fetches and stores only a few kilobytes.

Such high-performance resource usage is achieved through various approaches to reduce disk consumption and network usage on engineers' workstations. SOS downloads just the data that's needed right now while keeping everything else as soft links to remote files. At the same time, all this is handled seamlessly and transparently. Each workstation is kept in perfect sync with the central repository whenever any file is changed.

The elements of its optimization are described below:

• Cache servers: The central repository is mirrored by cache servers at each global CoE site. Each cache server syncs itself with the central repository over high-bandwidth networks.
• Lightweight symbolic links: When an engineer downloads a design, instead of downloading terabytes of files, only lightweight symbolic links to them are created on the workstation. Each link references the relevant file in the local cache server. SOS keeps all this file referencing fully transparent to the EDA tools, the operating system, and the user. They see and work with the links as if they're normal files on a local disk.
• Copy-on-write strategy: A file is downloaded to a workstation only when an engineer checks out a file for editing.
• Incremental updates: To avoid heavy network usage, large binary files are uploaded to the cache server incrementally.

Integrated version control

Figure 6. SOS version control integrated with an EDA tool

The Keysight SOS user interface has built-in version control that supports even binary formats like schematic and layout files. It also seamlessly integrates version control into popular EDA tools like:

• PathWave Advanced Design System
• Cadence Virtuoso Studio
• Synopsys Custom Compiler
• SiemensEDA Pyxis

This deep version control integration enables every engineer in any global CoE to see the same real-time status and details like the:

• subsystems or components that have been changed by other teams
• engineer who is currently working on a particular transistor cell, schematic, layout, component, or subsystem
• latest version of any item
• versions on their workstation

Figure 7. Visual highlighting of design changes by Visual Design Diff (VDD)

Additionally, Visual Design Diff enables engineers to graphically visualize the changes made in a schematic or layout. For each change, it can generate an impact analysis report to keep schematic and layout engineers in sync.

Deploy Keysight SOS as your chip's global design platform

This blog explained the need for global CoEs and the challenges of having them collaborate.

Keysight SOS offers factual, field-proven answers to all these challenges. Semiconductor companies that use SOS have seen dramatic boosts in their engineering lifecycle efficiency, global collaboration, design quality, product success, competitiveness, and cost savings.

Contact us for deep expertise on setting up your global design platform for semiconductor chips.