Design Data Management Inside VS Code With Keysight SOS

Key takeaways:

Design tools and version control tools in traditional chip design workflows involve many productivity bottlenecks that have not been sufficiently addressed.
The Keysight SOS platform addresses major productivity, data management, and collaboration challenges in chip design workflows.
The Keysight SOS Visual Studio Code extension brings the benefits of the Keysight SOS platform to the popular code editor, empowering digital design teams.

Digital chip design teams increasingly use modern, lightweight development environments such as Visual Studio Code (VS Code), a standard workspace offering both extensibility and familiarity.

While design work happens in the editor, engineering data management (version control, governance, and collaboration) typically lives in separate tools. This disconnect creates friction, reduces visibility, and slows down engineering teams.

In this blog post, discover the key bottlenecks of digital chip design workflows. Learn how Keysight SOS addresses them by bringing design data management directly into Visual Studio Code, unifying design and data workflows. Understand how it enables engineers to manage versions, collaborate, and maintain governance without leaving their daily working environment.

What are some key market drivers and trends impacting chip design workflows?

Traditional chip design workflows and tools are evolving due to increasing design complexity, growing data volumes, increasingly distributed teams, greater demands for governance and traceability, and the emergence of AI-ready workflows.

Increasing design complexity

The constant demand for more capable chips across industries is driving increasing design complexity. Many functions are tightly integrated onto a single platform through advanced architectures such as systems-on-chip (SoCs) and modular system-in-package configurations that combine multiple dies or chiplets.

Some relevant aspects of modern designs are outlined below:

Evolution of chiplets and multi-die systems: To mitigate the escalating costs of advanced process nodes, SoC design is evolving from monolithic, single-die designs to modular, chiplet-based, multi-die designs. Some of those modules may be third-party specialized intellectual property (IP) cores.
Heterogeneous domain integration: Capabilities such as digital logic, analog, mixed-signal, and radio-frequency (RF) transceivers are integrated on a single SoC.
Intricate IP dependencies: To shorten design cycles, IP cores, which are already pre-designed and pre-tested, are reused by multiple projects. This creates complex, deeply nested, hierarchical dependencies across different subsystems and projects.
Diverse, fragmented toolchains: The design and verification workflow requires orchestrating numerous specialized, standalone electronic design automation (EDA) tools for simulation, synthesis, placement, routing, and physical verification. Engineers must wrangle large volumes of data — related to simulation, verification, and multiphysics (e.g., electro-thermal) — and data formats between incompatible tools. Significant workflow fragmentation is the unwanted outcome.

Growing design data volumes

Figure 1. Typical data storage volumes and number of files

Increasing system design complexity also causes design data volumes to grow rapidly. Each SoC variant typically requires about one to two terabytes of storage. Hundreds of thousands of files per project are common nowadays, with contributions from dozens of component subprojects. Many files are several gigabytes in size, especially binary schematic and layout files.

Growing multi-site collaboration between distributed teams

As IC design workforces become globally distributed across different countries, time zones, and business units, collaboration becomes more difficult.

The geographic separation introduces network latency that can affect productivity and time-to-market. Transferring massive project files between sites means high bandwidth consumption and costs.

Expanding need for regulatory compliance, traceability, and governance

Experiences, insights, and feedback over time have led to increasingly stringent functional safety standards in safety-critical sectors such as automotive, aerospace, and defense. Organizations must comply with rigorous standards, such as the International Organization for Standardization (ISO) 26262 functional safety standard for road vehicles and the Design Assurance Guidance for Airborne Electronic Hardware (DO-254).

Additionally, geopolitical risks and export regulations demand strict data governance.

All this necessitates end-to-end digital thread traceability, including:

complete audit trails of who changed what, when, and why
strict role-based access permissions, geofencing, and automated release approval workflows to prevent data leakage and ensure compliance

In semiconductor engineering data management, CAD data management includes preserving CAD files, CAD tools, tool configurations, simulation models and results, test plans, verification results, and supporting documents throughout the integrated circuit (IC) development lifecycle.

Evolving toward AI-ready engineering workflows

The semiconductor industry is adopting artificial intelligence (AI), agentic AI, and machine learning for layout generation and predictive verification.

However, AI algorithms are less effective when trained on unstructured, disorganized, or inconsistent data with missing metadata.

So, design teams are adopting an organize-before-you-optimize paradigm. Traditional design data is cleaned and normalized into metadata-rich repositories. This ensures complete lineage tracking, enabling historical design data to be safely and reliably fed into machine learning pipelines and AI agent workflows.

What pain points are digital IC engineers facing?

Figure 2. Productivity bottlenecks in chip design

As these trends reshape IC development, design and verification engineers face several productivity bottlenecks in their day-to-day workflows.

Disconnect between the design environment and data management tools

Design data management (such as version control, revision tracking, and dependency mapping) has traditionally been done using separate tools, separate windows, and separate mental models from the primary IC design environments.

To perform routine data operations, such as checking in a file or updating an object status, engineers must leave their design tools and switch to a separate command-line terminal or graphical user interface (GUI) application. Focus and productivity suffer from frequent context switching between code editors, command-line tools, and visualization GUIs.

Diverse user interfaces

Existing tools have very different user interfaces and user experiences:

Primary design environments, such as Virtuoso and Keysight ADS, are often GUI-based.
For writing register transfer level (RTL) code in languages like VHDL/Verilog/SystemVerilog, some text editors, such as Vim, have terminal user interfaces (TUIs). In contrast, others, such as Emacs, have both GUIs and TUIs.
Version control tools such as Git have command-line interfaces with difficult-to-remember options.
Language and tool documentation are in different places and formats — some online, some through F1 help, and some in document formats.
Tools such as JIRA, Bugzilla, and Slack are browser-based web applications.
Many simulation, synthesis, and verification tools are available on remote servers and are typically accessed via secure shell (SSH) clients such as PuTTY.
Custom Python or Tool Command Language (TCL) scripts are executed using the built-in shells of EDA tools or in their own separate integrated development environments (IDEs).

This diversity hampers developer productivity and discourages workflow automation. Basic developer conveniences such as autocomplete and context help are not available.

Difficulties in tracking changes and ensuring design integrity

The absence of a single source of truth is a critical pain point in the industry. A single source of truth for all design data and decisions for a chip across space (multiple sites) and time (the chip's lifecycle) is critical.

One challenge is adapting general-purpose revision control tools such as Git to timely multi-site synchronization, large binary files, and specialized EDA workflows. For example, syncing gigabyte-sized binary files (such as schematics, layouts, and simulation waveforms) using Git is very inefficient in terms of storage and network bandwidth.

This drawback puts overall design integrity at risk. Remote teams may inadvertently work on older design versions, introducing incompatibilities. Without a global file-locking mechanism, two engineers may modify the same design cell simultaneously, causing one's changes to silently overwrite the other's upon merging.

Lack of real-time visibility across distributed teams

Another consequence of lacking a synchronized single source of truth is that changes to a component cell may not reach all dependent projects, designs, or teams in time. Without a reliable mechanism for communicating those changes, downstream effects may not be identified until late in the workflow.

Yet another problem with not having a single source of truth is that nuanced knowledge about designs and design decisions becomes siloed. As a result, organizational memory about a design becomes patchy over its lifecycle.

In safety-critical industries like automotive and defense, where a chip's lifecycle typically spans decades, such knowledge gaps over time can lead to significant operational, compliance, or maintenance risks.

Missing metadata and traceability

General-purpose data management tools don't capture crucial semiconductor-specific metadata such as process design kit (PDK) versions, process nodes, tool origins, or simulation instructions. Engineers often have to manually track such design context, and the quality of that tracking over time depends critically on how disciplined each engineer is.

Error-prone data transfers and format conversions

Because the tools don't talk to each other natively, engineers often resort to manual file exports/imports, zipping directories, custom data conversion scripts, and copying data via clipboard, which increases the likelihood of human error, data corruption, and security leaks.

Disconnected workflows across design domains

Figure 3. Mixed-signal chip design steps

Modern SoC designs require tight integration between the digital domain (including steps such as RTL coding and synthesis) and the analog domain (including schematics and layouts).

However, due to tool limitations, digital teams and analog teams have traditionally used entirely separate, disconnected data repositories. Such siloing makes mixed-signal integration highly complex, requiring manual coordination via inefficient channels like email, which creates major bottlenecks and increases tapeout and silicon re-spin risks.

How is data management in the code editor a paradigm shift?

One approach is to bring design data management into an extensible code editor that can integrate specialized tools and workflows. Visual Studio Code, or VS Code, provides such an environment.

VS Code as the central workspace

Figure 4. Visual Studio Code

The growing use of VS Code for hardware design reflects its flexibility across digital IC development, verification, scripting, and automation.

Compared with traditional tools, VS Code offers several advantages as a workspace for digital IC design and verification engineering. These include:

High extensibility: One reason for its popularity as a code editor and IDE across multiple industries is its powerful extensibility. It provides fine-grained control over many aspects of the software development process. From customizing the interface to automating end-to-end development workflows, extensions can support a broad range of engineering tasks.
Broad extension ecosystem: Free and paid extensions support VHDL, SystemVerilog, Python, TCL, and C++/SystemC for High-Level Synthesis (HLS), with features such as autocomplete, contextual assistance, Universal Verification Methodology (UVM) support, and waveform visualization.
Administrative control: For security, VS Code enables enterprises to control the extensions that their developers are allowed to use.
Built-in version control and metadata extensions: It enables integration with version control tools like Git and Perforce. Rich metadata capabilities can also be implemented using custom extensions.
Support for all popular operating systems: Unlike many traditional semiconductor design tools, which require specific operating systems, VS Code supports Windows, macOS, and Linux distributions.
Support for remote environments: In the IC design field, many tools run on remote machines, either for performance reasons or to maintain data integrity and confidentiality. They are often accessed over secure networks through SSH or virtual private networks. VS Code's seamless integration with remote environments enables their usage without frequent context switching.
Open source: VS Code is built on an open -source codebase and common web technologies such as TypeScript and Node.js, providing a flexible foundation for customized development workflows. A chip design organization can easily customize the entire IDE in proprietary ways if needed.
AI-ready design workflows: VS Code supports AI-assisted and agent-based development workflows.

How does Keysight SOS improve IC design productivity?

Keysight SOS is a purpose-built platform for IC and electronic design data management (DDM), including EDA version control, design traceability, governance, and collaboration. Unlike manufacturing-focused MRP systems, Keysight SOS is built around electronic design files, metadata, dependencies, revisions, and EDA tool integrations.

Its key capabilities include:

a centralized single source of truth for all design data
unified engineering data platform for governance, design traceability, and collaboration
integration of data management and metadata features with popular EDA tools
high-performance multi-site synchronization through SOS Enterprise for timely visibility into design status and dependencies across distributed teams
document management for all design documents

Single source of truth

Keysight SOS provides a centralized DDM platform that serves as a unified system of record for all design artifacts, including RTL code, simulation scripts, simulation results, synthesis results, route files, and more. This single source of truth engineering approach gives teams a consistent, governed view of design data, revisions, dependencies, and project status across tools and sites.

To achieve this at the scale of terabytes of text and binary data without high latencies and network loads, it provides:

site-local repositories that allow teams to collaborate at local speeds without conflicts and sync with other sites efficiently
use of symbolic file links on developer workstations instead of actual files and downloading actual file data only when needed
efficient version control, differencing, and merging for text and binary formats

Unified platform for data, governance, and collaboration

Keysight SOS provides centralized data storage, real-time visibility, traceability of changes, metadata integration, and built-in collaboration tools.

Domain-agnostic data management

Keysight SOS facilitates unified centralized DDM for all domains — digital, analog, mixed-signal, and RF. All teams can collaborate on its unified platform irrespective of their specialization.

Printed circuit board (PCB) designs can also be managed using Keysight SOS.

AI-ready architecture

Keysight SOS structures, tags, and versions design data as consistent, traceable, metadata-rich information that can support AI model development and agentic workflows.

How is Keysight SOS integrated into Visual Studio Code?

Figure 6. Keysight SOS VS Code extension

Keysight SOS has a companion VS Code extension that brings key design data management capabilities directly into the VS Code workspace. It enables version control and data management within the editor without context switching, governance and traceability, and real-time design-status visibility across collaborators.

SOS version control

Figure 7. SOS version control

The extension enables a familiar local staging workflow for reviewing, staging, and committing intermediate snapshots of edits before pushing them to the SOS repository. Alternatively, engineers can bypass staging and perform SOS check-ins directly.

Right-click file actions can be triggered directly from the file tree, allowing developers to create, check out, check in, discard, delete, or reanalyze any object.

Work area labels and revision search orders (RSO)

Figure 8. Labels and RSO

From the status bar, users can update the work area to specific points in time.

Labels (or tags) are human-readable aliases assigned to specific revisions (e.g., "design_done", "Gold"). The RSO is a priority list of tags that controls which revision of each object (such as a cell, schematic, or configuration) is retrieved during a populate or update operation, and it is visible to EDA tools. Together, they automate design handoffs between functional roles without manual coordination via email-based notifications, file transfers, or ad hoc coordination among design, layout, and verification engineers.

The extension allows selecting, ordering, and applying labels or adding stop clauses to the RSO.

Real-time visibility

Figure 9. Real-time visibility through visual indicators

Dynamic color-coded indicators propagate up the workspace file tree to instantly show project status (e.g., what has changed, which revision is active, which files are locked, unmanaged, or not on the latest revision).

Edits made by collaborators are highlighted in real-time using gutter indicators. Blue lines indicate changes, green indicates additions, and red indicates removals.

File locking

The VS Code extension uses visual markers to indicate file permissions, object ownership, and file locks as managed by the underlying SOS engine. If another user locks an object, other engineers can still view its contents or branch from it. Concurrent checkouts are blocked by default, but a configuration flag enables parallel editing.

Visual differencing

Figure 10. Visual differences

Users can compare changes line-by-line or block-by-block and selectively revert specific blocks of code within the editor.

Governance and traceability

The VS Code extension supports role-based access controls and brings governance and design traceability into the editor.

What are some use cases of the Keysight SOS VS Code extension?

Below are some illustrative use cases where Keysight SOS and its VS Code extension are beneficial.

Teams needing EDA-native version control

Git- or Perforce-based environments may still require additional scripts, integrations, and manual processes to manage EDA-specific metadata, dependencies, binary files, and governance. Keysight SOS provides high-performance version control purpose-built for electronic design data.

Its VS Code extension provides familiar version control actions and indicators for all files. Behind the scenes, it relies on the SOS server's high-performance techniques. For example, SOS can represent design files as symbolic links and download the underlying file data when the file is opened or requested by a workflow.

Mixed-signal teams consolidating workflows

Keysight SOS and its VS Code extension allow all teams and data to be managed centrally and consistently. Mixed-signal, analog, and RF teams can manage those domains through a more unified repository strategy. The extension enables seamless integration with other tools such as ADS and Cadence Virtuoso.

Labels and RSOs enable automated handoffs between functional domains, ensuring everyone works from the correct versions.

Distributed teams needing collaboration

The VS Code extension enables distributed teams to collaborate efficiently through real-time indicators for current and stale versions, locked files, changes, and more.

How does the Keysight SOS VS Code extension support automation and AI-ready workflows?

Keysight SOS and its VS Code extension enable automation and AI-ready workflows as follows:

Automation: By integrating most tools in a single IDE, VS Code enables GUI-level automation and automation using application programming interfaces (APIs).
Foundation for AI-driven engineering: By storing all design information as normalized, structured, metadata-rich data, SOS enables AI model training on design data, retrieval-augmented generation based on design data, and agentic workflows for design and verification.
Data reuse and knowledge graphs: The SOS AI layer is an intelligence layer that enables MLOps pipelines, semantic search, knowledge graphs, and agent-ready memory.

What are the key benefits of Keysight SOS and its VS Code extension?

After migrating to Keysight SOS — Core or Enterprise — and installing its VS Code extension, design engineers and project managers can expect the following business and development benefits:

Faster time to market: By bringing routine design data management tasks into VS Code, the SOS extension reduces context switching, eases tool friction, and supports engineering productivity. It can also reduce the need for error-prone manual transfers between disconnected tools.
Fewer re-spins: Real-time visibility and change indicators reduce the risk of engineers working on stale versions. Dependency tracking can also help teams identify affected projects earlier and initiate the appropriate verification workflows, reducing the possibility of costly re-spins due to design errors.
Lower total cost of ownership: By reducing manual coordination, workflow fragmentation, and avoidable rework, Keysight SOS can help lower the total cost of managing complex digital IC design workflows.

Effective design data management with Keysight SOS

This blog post explained how Keysight SOS brings IC design data management to a popular tool like VS Code that developers are already using. With this simple approach, Keysight SOS mitigates several productivity bottlenecks and deeper issues prevalent in traditional design workflows.

Learn more about Keysight SOS engineering data management, or watch SOS for Visual Studio Code:Design Data Management for Digital Design Teams to see the workflow in action.

limit