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Four Considerations for High-speed Digital Design Success
Table of contents
- Signal Integrity: Learn 3 steps to understanding signal integrity of a digital channel.
- Power Integrity: Discover two key analyses for demystifying power integrity
- Thermal Effects: Boards are getting hotter. Learn more about where the heat is coming from.
- System Analysis: Tale a look at two applications where channel simulation is necessary.
As Complexity Increases, Holistic Design Is Necessary
High-speed digital standards are quickly evolving to keep pace with the data demand from emerging technologies such as 5G, the Internet of Things, artificial intelligence, virtual reality, and autonomous vehicles. Each generational change of high-speed computing standards provides new signaling features, faster data transfer rates, and smaller design margins. Faster speeds create new design challenges that require higher-accuracy simulation, new software tools, and more efficient workflows.
As a hardware engineer, your job is to design, verify, build, and test electronic products. Fail to adopt new design methodologies and you risk product failure caused by the degradation of high-speed signals in your printed circuit board (PCB). You also risk project delays, a skyrocketing budget, or jeopardizing your stellar reputation.
CONSIDERATION 1 Signal Integrity Problems Cause Performance Issues
Signal integrity (the quality of an electrical signal) is all around us. In a digital communication channel, signal integrity analysis is the study of electrical signals as they traverse PCB traces, vias, connectors, and other components. Signal integrity problems can cause havoc for digital designs, including performance issues, lower yield, and possible failures in the field. These are costly problems as they often go undetected until late in the design and test cycle.
The best time to simulate a PCB for signal integrity is after layout and before fabrication. Taking the time to simulate becomes more important as speeds increase. There are now more factors that can lead to signal integrity problems. Common problems that can arise include reflections at the interconnects (mismatched impedances), electromagnetic coupling between the traces, and grounding issues. If not addressed, these problems can lead to signal distortion and attenuation.
Signal integrity analysis and simulation save time and money in the long run because it reduces the risk of late-stage design failures and helps you maximize your design margin.
3 Steps to Understand Signal Integrity of a Digital Channel
Ideally, you should consider signal integrity from the time you draw the schematic until the board passes the final test. Testing your assumptions with simulation is the best way to verify the signal integrity of your channel. To do that, follow these three steps:
Step 1: Simulate the channel with an eye diagram
The signal travels from a transmitter to a receiver across the PCB. As it travels, traces, connectors, and cables introduce interference that degrades a signal in both amplitude and timing. An eye diagram can help you determine if the quality of the signal is still good enough when it reaches the receiver
Step 2: Find the root cause of degradation
Once you discover a signal integrity problem, you can use two main analyses to determine its root cause in your design.
- Mixed-mode S-parameters
- Mixed-mode S-parameters tell you information about the frequency response of the channel.
- Time-domain reflectometry
- Time-domain reflectometry uses reflected waveforms to provide information about the channel. It shows you spatial and timing information.
Step 3: Explore design solutions
Once you identify the root cause of your signal integrity problem, you need to consider what modifications you can make in your design.
Consideration 2 Predicting Power Integrity Early Is Paramount
Failing a compliance test at the end of the product design cycle is expensive. Retrofits with added filters and capacitors increase manufacturing costs. Design re-spins result in product delays and lost revenue. It is more effective to start early in the design phase to understand and mitigate potential power issues.
The objective of power integrity analysis is to ensure the drivers and receivers in your board get the voltage and current they need to operate correctly. To ensure power integrity, you want to avoid DC voltage drop (a measure of the voltage loss from current flowing through the resistance of the power and ground plane).
Early Design Exploration Is Key
Three main factors drive power integrity challenges and increase the impact of DC voltage drop.
- Higher device integration – More integration creates denser routing, resulting in higher current density in the power network and more DC voltage drop.
- Lower supply voltages – A 10% tolerance on 1 V is a tighter specification to meet than a 10% tolerance on a 1.2-V requirement, thus increasing the impact of voltage drop.
- Smaller form factors – Less real estate on the PCB results in less space for wide power planes, causing DC voltage drop.