When Design Data Becomes a Liability (and What to Do About It)

When design data becomes a liability, productivity suffers. Discover how Keysight SOS simplifies IP management and boosts engineering efficiency.

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Key takeaways:

A chip designer not only has to solve tough electronic problems, but they also have to worry about development process issues like:

Such questions about version control, IP metadata, and design data can further slash productivity in an industry that's already worried about it due to growing design complexity.

At Keysight, we help semiconductor innovators accelerate time-to-market and reduce risk by giving them complete control over their design data and IP workflows. Our SOS platform is purpose-built to meet the demands of modern chip complexity — no matter the application.

In this article, we shine a spotlight on efficient design data management and IP integration with chip engineering lifecycle management (ELM) to optimize productivity and time-to-market.

Why are chip design data and IP management so important?

In our earlier post on semiconductor engineering lifecycle management, its scope and responsibilities were depicted as shown in the illustration below.

Figure 1. Scope of engineering lifecycle management

Among these, design data management (DDM) provides a single centralized source of truth for all information about every integrated circuit (IC), system-on-chip (SoC), or chiplet.

IP management is a subset of DDM that focuses on tracking the use of IP blocks in a company's designs.

These two aspects are critical for effective ELM because all the other functions depend on them. Let's look into these dependencies in detail.

Design collaboration

Systematic design data management is critical for efficient collaboration between all the research, development, simulation, and verification teams that are often globally distributed. For every item stored in the DDM, features like issue tracking, revision control, and thorough documentation are equally critical and must be facilitated by the DDM's workflows.

Model-based systems engineering

The shift-leftsystems design approach encourages engineers to identify and mitigate all issues — like chip heating and electromagnetic interference — as early as possible by simulating them.

One of DDM's important responsibilities is the preservation of all the simulation models, test plans, results, and documentation over the entire development lifecycle.

Change management

Modern SoCs are layered hierarchies consisting of dozens of smaller ICs, each with complex design, simulation, and verification procedures. Whenever any constituent circuit is changed, it may have adverse effects on other parts of the SoC or the overall performance. So, tracking all design or performance dependencies and cascading automated verification sequences for them is an essential responsibility of DDM and IP management.

Requirements, traceability, and configuration management

All the requirements, specifications, and engineering change requests of a chip must be captured and searchable — from its earliest inception stages until end-of-life — to preserve institutional memory and past knowledge about its design decisions. Equally crucial is the systematic tracking of the lineage of every component in the chip's hierarchy so that all stakeholders can find out exactly which component version was used in each chip version.

The DDM facilitates such knowledge management.

Compliance management

Every jurisdiction and industry imposes regulations and standards that restrict the design space of chips. Regulations related to sanctions, arms trade, and defense procurement restrict technology transfers to or from other countries. Sustainability regulations may restrict materials and manufacturing techniques. Additionally, these rules change often.

For remaining compliant throughout a chip's lifecycle, the DDM and IP management facilitate granular compliance and IP usage tracking at all stages.

What are some common data and IP management challenges in the semiconductor industry?

Good design data and IP management must not only facilitate all the above ELM responsibilities but do so accurately, efficiently, and securely to maximize engineering productivity. As early as 2013, McKinsey had observed that the increasing complexityof chip design was reducing development productivity and increasing engineering costs. The situation now is even worse due to challenging demands from the downstream industries.

Semiconductor companies must exploit every possible optimization in their product development to maximize productivity. To do so, their engineering lifecycle management solutions must overcome several challenges outlined below.

Scalability issues due to high data volumes

file sizes for MMIC, Analog, PDK, digital design

Figure 2. Chip design data volumes

The first big hurdle is the sheer size of chip design data. Each SoC design and variant requires 1-2 terabytes of storage. Managing so much data with speed and responsiveness complicates the storage, network transfer, and version control implementations.

Version control challenges

Common version control systems (VCS), like Git, are not ideal for chip design. They don't implement version control in ways that are optimized for the chip design ecosystem. Some common challenges are listed below:

IP reuse obstacles

Reusing pre-designed and pre-verified IP cores can significantly speed up the chip engineering process. However, challenges include:

Siloed knowledge

The semiconductor industry's culture of need-to-know secretiveness to protect intellectual property can lead to knowledge silos even within a company. An engineering team may already know a lot about a particular IP core, but the silo culture prevents that precious knowledge from organically spreading to other project teams and increasing overall productivity.

Documentation challenges

Chip design involves plenty of internal and partner documents like:

Each of these may have multiple versions. Finding and retrieving the exact document and version that a designer needs requires highly capable document management and information retrieval features.

Inefficient manual processes

Many companies continue with inefficient manual workflows for design change reviews, approvals, IP discovery, collaboration, procurement, and more.

What are some common engineering challenges in automotive chip design?

Automotive chip design involves additional challenges like these:

What are some common engineering challenges in chip design for 5G/6G telecommunications?

Similarly, chips used in 5G/6G antennas, base stations, core switches, and non-terrestrial networks are mixed-signal devices that involve both radio frequency IC and high-speed digital IC designs. Data and IP management for such mixed-signal designs involve various unique challenges listed below:

How do Keysight SOS address chip ELM challenges?

To address all these challenges, Keysight offers a dedicated design data management and IP management platform for semiconductor companies. Let's understand how they address all the above challenges of semiconductor engineering lifecycle management.

Comprehensive design data management

Figure 3. Keysight SOS

Keysight SOS stores — in a centralized project repository — all the requirements, specifications, intermediate design files, tapeout files, technical documents, embedded software development, simulation models, test management, legal documents, and regulatory reports related to a chip design. They can be from internal teams and partner companies.

All this engineering data can be arranged under subsystems and components in a natural hierarchy for convenient management. Granular access control is supported through user roles, groups, and permissions per user per item.

Efficient multi-site design collaboration

By centralizing the storage, Keysight SOS becomes a single source of truth for a chip design. All teams across the world see the same files and versions.

Engineers download a project's files to workspaces on their workstations. Even if the design is a couple of terabytes, this is an extremely fast operation that downloads only a few kilobytes. Keysight SOS uses various copy-on-write and caching strategies to minimize disk consumption on engineers' workstations. It downloads only what's needed but also keeps the workstations in perfect sync with the central repository whenever any changes are made.

Integrated version control

Figure 4. SOS version control integrated with an EDA tool

Versions are shown in the Keysight SOS user interface. Version control is also seamlessly integrated into EDA tools like:

All teams around the world can answer questions like these in real time:

Figure 5. Visual highlighting of design changes by Visual Design Diff (VDD)

In addition, Visual Design Diff enables engineers to see the changes made in a schematic or layout graphically. It also generates impact analysis reports to keep schematic and layout engineers in sync.

High-performance architecture

The speed and responsiveness of Keysight SOS are due to a unique architecture with highly optimized storage and network resource usage. It consists of the following:

Streamline your chip engineering lifecycle management

In this blog, we showed how design data and IP management are critical for high-quality semiconductor ELM, the challenges therein, and their mitigations by Keysight's software.

Contact us for engineering insights into streamlining your chip design processes.