Choose a country or area to see content specific to your location
White Papers
In the beginning there was transient simulation. Ensuring functional chip-tochip links in a system meant performing a time-domain simulation with a SPICE simulator. The result was a time-domain waveform that was evaluated during post processing for signal integrity (SI). The main task was to measure the eye diagram, usually assuming a perfect clock as the phase reference (Figure 1). Due to rising signaling speeds and decreasing timing margins, the task was made more challenging when it became necessary to account for other effects. For chip-to-chip communication systems that used an embedded clock, the phase-locked-loop behavior was taken into account and the jitter simulated or subtracted from the remaining timing margin of the eye. For source synchronous signals, the clock was also simulated and used for setup/hold calculations or data eye generation. In addition to link architecture changes, simulation accuracy had to be improved to account for the decreased margins, resulting in complex modeling that took into account even small parasitics.
Unlock Content
Sign up for free
*Indicates required field
Thank you.
Your form has been successfully submitted.
Note: Clearing your browser cache will reset your access. To regain access to the content, simply sign up again.
×
Please have a salesperson contact me.
*Indicates required field
Thank you.
A sales representative will contact you soon.