Device Modeling Flow

The diagram shown in Figure 1 below represents the typical flow followed by device modeling engineers. Device Modeling engineers typically use dedicated on-wafer layouts to facilitate probing of single devices such as transistors or passive devices (e.g. inductors or resistors). These layouts depend on the type of measurements (DC, CV, RF or Noise) and the probing method (RF probes or probe cards).

Figure 1. The typical flow followed by device modeling engineers.

The first step in the Modeling flow involves Data measurement and analysis. The procedure to select a typical die to be used for device modeling measurements varies depending on the process development stage. If the process is mature, Process Control Measurements (PCM) data from the inline fab are generally used as a reference to determine the typical or golden die. This is the die whose devices are predicted to be the closest to the process statistical typical specifications. Sometimes device modeling engineers will also run PCM measurements on a wafer or lot of wafers to determine the typical die. Once the die and the corresponding set of devices have been identified via statistical analysis, then a comprehensive and accurate set of measurements are made over at least three temperatures. These measured data will later be used for device model extraction. Other measurements such as ring oscillator, load pull, gain compression and intermodulation, etc. are usually made to verify that the models extracted from linear DC and S-parameter data are accurate under the conditions that are closest to the final applications (such digital circuits for digital processes or amplifiers, mixers for RF processes). To learn more about measurement challenges and solutions, refer to Device Characterization and Data Analysis.

Model extraction methods vary depending on the technology and the device model. In general, the device modeling software will provide a set of tools and methodologies to apply to extract the parameters of the model such that the model simulation data matches the measured data. These tools include advanced graphics, links to circuit simulators, optimizers and manual tuners. Especially in the case of RF modeling, custom programming may be required to de-embed S-parameters by parasitic effects. Most compact models use mathematical equations to describe how currents and charges vary as a function of the applied voltages and temperature. Some of these equations are physics-based, such as most BJT or CMOS models; others are empirical, such as most compound semiconductor FET models. The challenge for the modeling engineer is to implement a repeatable and robust procedure to extract the parameters of the model such that the mathematical model representation (e.g. simulation) will match the measured data. Sometimes, engineers run into model limitations and are required to modify existing models to achieve the desired accuracy. To learn more about modeling visit the RF Compound Semiconductors Modeling and the Advanced Silicon Modeling pages.

Model validation is an important task performed by modeling teams to ensure the quality of modeling libraries before these are deployed by internal or external customers. Besides doing model verification to confirm the accuracy in comparison to measured data, models must also be tested for robustness by running simulations over extended bias, geometry and frequency conditions. Dedicated software can automate this task, which is tedious if done manually, and automatically detect and report issues by running exhaustive simulation tests. To learn more, refer to the Model Validation page.

Device Modeling libraries are then integrated into Process Design Kits (PDKs) along with layout and design rules. PDKs are usually specific to circuit simulator flow such as Advanced Design System (ADS) Design Kits or Cadence (Spectre) PDKs. PDK validation is a challenging and time consuming task because every time a new simulator software version is released or a Design Kit is updated, an extensive set of sample designs are re-verified by comparing new and old simulated results.