Column Control DTX
Boundary Scan DFT Guidelines for Good Test Coverage

Boundary Scan DFT Guidelines for Good Test Coverage

Notas de Aplicação

Introduction

Let’s start with a brief preface into the ‘why’ and ‘what’ of Boundary Scan and later delve into the crux of this paper of Board Design for Testability (DFT) guidelines.

Boundary Scan is also known as IEEE standard 1149.1. This standard was formalized in 1990 by a group called Joint Test Action Group (JTAG). This came into existence due to the increasing complexities in validating the IC design rules and testing on printed circuit board assemblies (PCBAs). Advancements in IC technology and device packaging led to miniaturization of chips. With massive miniaturization, the access to chip for its testing became limited. Convergence led to having multiple chips (with minimal access) on the same PCB. All these aspects posed:

  • Lots of challenges in validating the IC design rules
  • Extreme difficulty in testing these PCBs

×

*Indicates required field

*Required Field
Preferred method of communication? Change email?
Preferred method of communication?

By clicking the button, you are providing Keysight with your personal data. See the Declaração de privacidade de Keysight Para obter informações sobre como usamos esses dados.

Thank you.

A sales representative will contact you soon.

Column Control DTX