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Advanced Memory Buffer (AMB)

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敘述

Fast, accurate and simplified testing

The new fully buffered DIMM (FBD) interface uses a gigabit, multiple-serial connection between the memory controller hub/CPU and an advanced memory buffer (AMB), for higher memory bandwidth to supply increasing CPU speeds. The FBD interface is a point-to-point bus with up to 10 south-bound lanes (relaying commands from the CPU to the memory) and 12 to 14 north-bound lanes (transporting data back to the CPU). Each lane runs at up to 4.8 Gb/s in the first generation.

With speed rates up to 4.8 Gb/s, and in the future up to 9.6 Gb/s, signal integrity is degraded by the bandwidth limitations of the transmission medium. Test engineers are required to measure & characterize jitter (RJ, DJ, and TJ) and parallel output timing on the parallel receiver and transmitter lanes, as well as receiver jitter tolerance.

AMB

Compatible with J-BERT N4903A and ParBERT 81250

The ParBERT 81250 can stimulate and analyze the multi-lane point-to-point interface. The data sequence editor even lets you control different states of the AMB chip to prepare the AMB for testing. To test receiver jitter tolerance, each pattern generator’s delay control input lets you inject input stress for receiver lanes.

Parallel and synchronous transmitter analysis is provided with the output timing measurements and RJ, DJ, TJ measurements. Some AMB devices can be set in test state via a com interface. These devices can be conveniently tested by the J-BERT N4903A.

AMB

Benefits of Keysight‘s ParBERT 81250

  • Characterize quickly and accurately by testing receivers and transmitters on several lanes at the same time
  • Set different states of the AMB chip easily with the ParBERT data sequence editor
  • Enjoy the convenience of a complete test solution provided with fixtures, probes and oscilloscopes

Benefits of Keysight J-BERT N4903A

Simplified testing through:

  • Integrated and calibrated jitter sources
  • Sub-rate clock
  • Quick eye analysis