W2232BP ADS Core, Circuit Sim, Ptolemy, Mature Wireless Libraries Bundled
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主要技術規格
The ADS Core, Circuit Sim, Ptolemy, Mature Wireless Libraries Bundle is recommended for:
- RF/Mixed-Signal Silicon RFIC Design and Verification
敘述
The ADS Core, Circuit Sim, Ptolemy, Mature Wireless Libraries Bundle funtionality is shown in the table below.
| Model Number | Name | Description |
|---|---|---|
| W2200BP | ADS Core | Provides essential RF and microwave design capabilities in a highly productive enterprise schematic design environment. Fast linear simulation, comprehensive filter and passive circuit synthesis. |
| W2300EP | Harmonic Balance Element | Provides analysis of non-linear circuits excited with multi-tone sources, and extensive, preconfigured simulation setups useful in amplifier, RF, microwave, oscillator and custom circuit designs. |
| W2301EP | Circuit Envelope Element | Provides efficient simulation technique for complex digitally modulated RF signals in addition to templates for designing linearizers, RF Systems, and PLL Systems. |
| W2302EP | Transient Convolution and Channel Simulation Element | Advanced time-domain Element that includes Transient Simulator (SPICE transient analysis including HSPICE and Spectre compatibility modes), IBIS Model Library, Convolution Simulator (creates time-domain models from frequency domain data), Channel Simulator (includes bit-by-bit and statistical modes, eye diagrams and BER contours, IBIS AMI), Front Panels (including jitter decomposition), Encrypted HSPICE Co-simulation interface, and Broadband SPICE Model Generator. |
| W2361EP | Ptolemy Element | System-level simulation and design solution for synchronous and timed-synchronous dataflow, model analysis/optimization, HDL Cosim, and Digital, 802.xx, Antenna, Radio and Bluetooth design models. |
| W2363EP | Mature Wireless Libraries Element | Provides PHY level systems/models that conform to Wireless Connectivity Standards providing “Golden Reference” models to simulate and verify algorithm and system performance early in the design phase. |
