The last order date for the A-version of the J-BERT N4903A high-performance serial BERT will be April 30, 2010. The recommended replacement product is the J-BERT N4903B, which offers more jitter injection capabilities, half-rate clocking support, built-in CDR and cleaner output performance at a comparable price. N4903A software and hardware upgrade options can be ordered until April 30, 2011. Upgrades from the N4903A to the B version are possible by ordering N4903B-UAB. J-BERT N4903B.
J-BERT N4903B High-performance Serial BERT The only complete jitter tolerance test – now for next generation of forwarded and embedded clock designs such as QPI, PCIe, DisplayPort, SATA, USB, FB-DIMM, Fibre Channel, 10GbE.
The Keysight J-BERT N4903A High-Performance Serial BERT provides the only complete jitter tolerance test solution for characterization of serial gigabit devices.
The J-BERT offers complete, integrated and calibrated jitter composition for stressed eye testing of receivers up to 12.5 Gb/s.
Automated and compliant jitter tolerance testing allows quick and accurate characterization for all popular serial bus standards, such as PCIeTM, SATA, FB-DIMM, Fibre Channel, CEI, Gigabit Ethernet and XFP/XFI.
The J-BERT matches to latest serial bus interfaces perfectly with its ability to analyze undeterministic traffic, generate complex pattern sequences, subrate clock outputs. Clockless and differential interfaces can be tested.
The J-BERT is an expandable, future-proof BERT platform where all options can be configured to the current test needs and upgraded later when those needs change.
It is the ideal choice for R&D and validation teams who characterize and stress chips and transceiver modules with serial I/O ports up to 12.5 Gb/s.