Choose a country or area to see content specific to your location
Confirm your country to access relevant pricing, special offers, events, and contact information.
PRODUCTS AND SERVICES
- Spectrum Analyzers (Signal Analyzers)
- Network Analyzers
- Logic Analyzers
- Protocol Analyzers and Exercisers
- Bit Error Ratio Testers
- Noise Figure Analyzers and Noise Sources
- High-Speed Digitizers and Multichannel DAQ Solutions
- AC Power Analyzers
- DC Power Analyzers
- Materials Test Equipment
- Device Current Waveform Analyzers
- Parameter / Device Analyzers and Curve Tracers
- Generators, Sources, and Power Supplies
- Modular Instruments
- Network Test and Security
- Network Visibility
- Additional Products
- All Products, Software, Services
What are you looking for?
PAM-4 Simulation and Design of Next Generation High-Speed Digital Links
As people use more applications on their phones, tablets, computers, and Internet of Things (IoT) devices, the network needed to deliver the data is constantly being upgraded. Four-level Pulse Amplitude Modulation (PAM-4) signaling is a leading contender for implementing the 56G lane data rate which will enable 400G links and fuel the next upgrade in network bandwidth.
PAM-4 is gaining traction for high-speed SerDes links over an electrical backplane, especially for designs attempting to deliver greater than 56Gbps throughput. Doubling data rates with traditional non-return to zero (NRZ) signaling is technically challenging due to the extraordinary signal loss at high frequencies. The alternative signaling technique, PAM-4, is to transmit at 28Gbaud, but with 4 amplitude levels (where each level represents 2 bits), effectively delivering 56Gbps throughput.
System Design Challenges
Conventional impairments such as jitter, noise, channel loss, and inter-symbol interference (ISI) have an unexpected behavior in a PAM-4 context. In addition to this, receiver architectures for PAM-4 introduce new concepts for system designers such as:
- 3 Slicer outputs with time-varying voltage thresholds (for deciding which amplitude level has been recieved)
- Individual Slicer Timing Skew (each Slicer's decision point can be offset in time from the other two)
- Multi-tap Decision Feedback Equalization (DFE)
- Clock and Data Recovery
The complex interaction of these new concepts influences specific design trade-offs for PAM-4.
The ADS channel simulation enables a comparison of PAM-4 versus NRZ technology. This example demonstrates the concept of price vs performance in PCB design. Cheaper
PCB materials with more loss and no-backdrilling of vias are more likely to exhibit resonances at higher frequencies. This channel may not support NRZ to 56Gbps, but
will support PAM-4 more easily, assuming that the resonances are higher in frequency than the main spectral content of the PAM-4 signal.
The Channel Simulation Solution
For the system designer attempting to compare NRZ to PAM-4 trade-offs, an immediate need exists to use PAM-4 IBIS-AMI models from SerDes vendors within their Channel Simulation. Through Keysight Technologies' continuing leadership in the IBIS Open Forum, Keysight EEsof EDA now offers support for the new IBIS v6.1 specification. Developed in collaboration with the industry's leading PAM-4 SerDes IC vendors, the ADS Channel Simulator provides a trusted bit-by-bit simulation engine for PAM-4.
Where to find more information:
- Download application note: PAM-4 Design Challenges and the Implications on Test
- How to Use a SERDES Channel Simulator for PAM-4 Simulations and Analysis Webcast
- Contact us for PAM-4 Simulation Models for TX/RX and a FREE trial license for ADS
- Get to know our 400G Design and Test Solutions
For more information on PAM-4 solutions from Keysight Technologies, refer to https://www.keysight.com/find/pam4