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PRODUCTS AND SERVICES
- Spectrum Analyzers (Signal Analyzers)
- Network Analyzers
- Logic Analyzers
- Protocol Analyzers and Exercisers
- Bit Error Ratio Testers
- Noise Figure Analyzers and Noise Sources
- High-Speed Digitizers and Multichannel DAQ Solutions
- AC Power Analyzers
- DC Power Analyzers
- Materials Test Equipment
- Device Current Waveform Analyzers
- Parameter / Device Analyzers and Curve Tracers
- Generators, Sources, and Power Supplies
- Modular Instruments
- Network Test and Security
- Network Visibility
- Additional Products
- All Products, Software, Services
Keysight enables innovators to push the boundaries of engineering by quickly solving design, emulation, and test challenges to create the best high-speed digital experiences. Whether you’re looking to optimize performance, or perform analysis, debug, and compliance testing, Keysight accelerates innovation with intelligent insights that reduce risk and speed time-to-market.
Join Keysight at booth 1039 or attend our Keysight Education Forum (KEF) to learn how we can help you accelerate your digital designs.
January 31 – February 2, 2023
Santa Clara Convention Center
5001 Great America Pkwy
Santa Clara, CA 95054
High-Speed Digital Innovations Start Here
Keysight’s technical experts and application engineers will demonstrate the most advanced design and test solutions, developed for solving today’s most difficult high-speed digital measurement challenges.
Stop by our booth on February 1 and 2 during expo hours between 11:00 a.m. - 6:00 p.m. to experience the demos.
Keysight Education Forum (KEF)
Great America K
We are pleased to offer you all 7 Keysight Education Forum (KEF) sessions free of charge. Keysight’s test and measurement experts continue with KEF 2023 to showcase undeniable leadership and commitment across the high-speed digital and semiconductor markets.
Wednesday, February 1 Sessions
8:00 a.m. – 8:40 a.m.
Advanced Testing Challenges at 32GBaud PAM4 with PCIe 6.0
8:55 a.m. – 9:35 a.m.
Advanced Jitter Transfer Measurements for PLL Characterization
11:10 a.m. – 11:50 a.m.
Next Gen Development in USB4 Version 2.0
11:55 a.m. – 12:35 p.m.
Intuitive Simulation and Measurement Workflow for Hardware Engineers
2:40 p.m. – 3:20 p.m.
Physical Layer Validation Challenges of Characterizing 100/200 Gbps/lane Designs
3:30 p.m. – 4:10 p.m.
How To Efficiently Build and Analyze Memory Bus to Meet DDR Specification
4:20 p.m. – 5:00 p.m.
Advanced Power Integrity Simulation and Measurement Tips and Tricks