Number on hex display	Rule code	Protocol error
00	FRAME_0	Whenever STOP# is asserted, the master must deassert FRAME# as soon as IRDY# can be asserted. (PCI Spec. Appendix C, Rule 12 e)
01	FRAME_1	Fast Back-To-Back is only allowed after a WRITE transaction or a Master abort. (PCI Spec. Sect. 3.4.2. Fast Back-to-Back Transaction)
02	IRDY_0	IRDY# must not be asserted on the same clock edge that FRAME# is asserted, but one or more clocks later. (PCI Spec. Sect. 3.3.1. Read Transaction - see timing diagram)
03	IRDY_1	FRAME# can not be deasserted unless IRDY# is asserted. IRDY# must always be asserted on the first clock edge that FRAME# is deasserted. (PCI Spec. Appendix C, Rule 8 c)
04	IRDY_2	IRDY# must be deasserted after last transfer or when FRAME# is high and STOP was asserted. (PCI Spec. Sect. 3.3.3.1. and 3.3.3.2.1, Rule 1)
05	IRDY_3	A transaction starts when FRAME# is sampled asserted for the first time - IRDY# must not go low when FRAME# is high. (PCI Spec. Appendix C, Rule 7)
06	IRDY_4	Once a master has asserted IRDY#, it cannot change IRDY# of FRAME# until the current data phase completes. (PCI Spec. Appendix C, Rule 8 d)
07	DEVSEL_0	DEVSEL# must not be asserted during special cycle or if a reserved command was used. (PCI Spec. Sect. 3.7.2. Special Cycle and Sect. 3.1.1. Command Definition)
08	DEVSEL_1	DEVSEL# must not be asserted when FRAME# is high or was sampled high on last clock edge. (for DAC DEVSEL# must be delayed by one cycle) (PCI Spec. Sect.3.3.1. Read Transaction - see timing diagram)
09	DEVSEL_2	Once DEVSEL# has been asserted, it cannot be deasserted until the last data phase has completed, except to signal target-abort. (PCI Spec. Appendix C, Rule 35)
0A	DEVSEL_3	If not already deasserted, TRDY#, STOP# and DEVSEL# must be deasserted the clock following the completion of the last data phase and must be tri-stated the next clock. (PCI Spec. Appendix C, Rule 12 f)
0B	TRDY_0	A target must assert DEVSEL# (claim the transaction) before it is allowed to issue any other target response. (TRDY#). (PCI Spec. Appendix C, Rule 34)
0C	TRDY_1	TRDY# must not go low the first clock after assertion of FRAME# in a read transaction (a turnaround cycle is necessary). (PCI Spec. Sect. 3.3.1. Read Transaction - see timing diagram)
0D	TRDY_2	Once a target has asserted TRDY#, it cannot change DEVSEL#, TRDY#, STOP# until current data phase completes. (PCI Spec. Appendix C, Rule 12 d)
0E	STOP_0	DEVSEL# must be asserted with or prior to the edge at which the target enables its outputs (STOP#). (PCI Spec. Appendix C, Rule 34)
0F	STOP_1	Once asserted, STOP# must remain asserted until FRAME# is deasserted; whereupon, STOP# must be deasserted. (PCI Spec. Appendix C, Rule 12 c)
10	STOP_2	Once a target has asserted STOP#, it cannot change DEVSEL#, TRDY#, STOP# until current data phase completes. (PCI Spec. Appendix C, Rule 12 d)
11	LOCK_0	LOCK# must be asserted the clock following the (first) address phase and kept asserted to maintain control. (PCI Spec. Appendix C, Rule 32 e)
12	LOCK_1	The first transaction of a locked access must be a READ. (PCI Spec. Appendix C, Rule 32 d)
13	LOCK_2	LOCK# must be released if RETRY is signaled before a data phase has completed and lock has not been established or whenever an access is terminated by target-abort or master-abort. (PCI Spec. Appendix C, Rules 32 f and 32 g)
14	CACHE_0	After HITM, CLEAN must be signaled before STANDBY (PCI Spec. Sect. 3.4.1. Arbitration Signaling Protocol)
15	CACHE_1	HITM must only be signaled after STANDBY (PCI Spec. Sect. 3.4.1. Arbitration Signaling Protocol)
16	PARITY_0	PERR# may never be asserted two clocks after address phase (or earlier in a transaction) or during a special cycle. During WRITE, PERR# may be asserted two clocks after IRDY#, during READ, PERR# may be asserted two clocks after TRDY#. (PCI Spec. Sect. 3.8.2. Error Reporting)
17	PARITY_1	AD[31 :: 0] address parity error (PCI Spec. Appendix C, Rule 37 b)
18	PARITY_2	A parity error has occurred, but was not signaled