!!!!    6    0    1  987023439  V10fe                                         

! Device           : tc5588
! Function         : Static RAM 8k x 8 MOS
! revision         : B.01.00
! safeguard        : high_out_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

warning  " This device has outputs that can be set in the high   "
warning  "   impedance state.  In order to test Output_Enable    "
warning  "   (pin 22) pullups are needed on Data_bus             "
warning  "   (pin 19,18,17,16,15,13,12,11)                       "

sequential

vector cycle  500n
receive delay 400n

assign   VCC         to pins  28
assign   GND         to pins  14

assign   Address_bus          to pins 2,23,21,24,25,3
assign   Address_bus          to pins 4,5,6,7,8,9,10
assign   Chip_Selects         to pins 26,20
assign   Output_Enable_bar    to pins 22
assign   Write_Enable_bar     to pins 27

assign   Data_bus             to pins 19,18,17,16,15,13,12,11
assign   Data_D0              to pins 11   !AT Added for minimum pin test.
assign   Data_D1              to pins 12   !AT Added for minimum pin test.
assign   Data_D2              to pins 13   !AT Added for minimum pin test.
assign   Data_D3              to pins 15   !AT Added for minimum pin test.
assign   Data_D4              to pins 16   !AT Added for minimum pin test.
assign   Data_D5              to pins 17   !AT Added for minimum pin test.
assign   Data_D6              to pins 18   !AT Added for minimum pin test.
assign   Data_D7              to pins 19   !AT Added for minimum pin test.

assign   NC                   to pins 1

power    VCC,GND

inputs    Address_bus,Chip_Selects,Output_Enable_bar
inputs    Write_Enable_bar

bidirectional  Data_bus
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.
bidirectional  Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test.

nondigital NC


family   TTL

format hexadecimal Address_bus,Data_bus

when     Chip_selects   is    "z1"   inactive Data_bus
when     Chip_selects   is    "0z"   inactive Data_bus
when     Output_enable_bar is "1"   inactive Data_bus
when     Write_enable_bar is    "1"   outputs  Data_bus
when     Write_enable_bar is    "0"   inputs   Data_bus

trace    Data_bus  to  Address_bus, Chip_selects, Output_enable_bar
trace    Data_bus  to  Write_enable_bar

disable  Data_bus    with  Output_Enable_bar   to  "1"
disable  Data_bus    with  Chip_Selects        to  "X1"
disable  Data_bus    with  Chip_Selects        to  "0X"
disable  Data_bus    with  Write_Enable_bar    to  "0"

set load on groups Data_bus to pull up
!***************************************************************
!***************************************************************

vector  Initialize_Inputs
   set   Address_bus          to "0000"
   set   Chip_Selects         to "01"
   set   Output_Enable_bar    to "0"
   set   Write_Enable_bar     to "1"
end vector

vector  Keep_Inputs
   set   Address_bus          to "kkkk"
   set   Chip_Selects         to "kk"
   set   Output_Enable_bar    to "k"
   set   Write_Enable_bar     to "k"
end vector

! Inputs

vector Address_0000
   initialize  to Keep_Inputs
   set   Address_bus          to "0000"
end vector

vector Address_0001
   initialize  to Keep_Inputs
   set   Address_bus          to "0001"
end vector

vector Address_0003
   initialize  to Keep_Inputs
   set   Address_bus          to "0003"
end vector

vector Address_0007
   initialize  to Keep_Inputs
   set   Address_bus          to "0007"
end vector

vector Address_000F
   initialize  to Keep_Inputs
   set   Address_bus          to "000F"
end vector

vector Address_001F
   initialize  to Keep_Inputs
   set   Address_bus          to "001F"
end vector

vector Address_003F
   initialize  to Keep_Inputs
   set   Address_bus          to "003F"
end vector

vector Address_007F
   initialize  to Keep_Inputs
   set   Address_bus          to "007F"
end vector

vector Address_00FF
   initialize  to Keep_Inputs
   set   Address_bus          to "00FF"
end vector

vector Address_01FF
   initialize  to Keep_Inputs
   set   Address_bus          to "01FF"
end vector

vector Address_03FF
   initialize  to Keep_Inputs
   set   Address_bus          to "03FF"
end vector

vector Address_07FF
   initialize  to Keep_Inputs
   set   Address_bus          to "07FF"
end vector

vector Address_0FFF
   initialize  to Keep_Inputs
   set   Address_bus          to "0FFF"
end vector

vector Address_1FFF
   initialize  to Keep_Inputs
   set   Address_bus          to "1FFF"
end vector

vector Address_3FFF
   initialize  to Keep_Inputs
   set   Address_bus          to "3FFF"
end vector

vector Address_7FFF
   initialize  to Keep_Inputs
   set   Address_bus          to "7FFF"
end vector

vector Address_FFFF
   initialize  to Keep_Inputs
   set   Address_bus          to "FFFF"
end vector

vector Chip_Selects_true
   initialize  to Keep_Inputs
   set   Chip_Selects          to "10"
end vector

vector Chip_Selects_false
   initialize  to Keep_Inputs
   set   Chip_Selects          to "01"
end vector

vector Chip_Select1_false
   initialize  to Keep_Inputs
   set   Chip_Selects          to "11"
end vector

vector Chip_Select2_false
   initialize  to Keep_Inputs
   set   Chip_Selects          to "00"
end vector


vector Output_Enable_true
   initialize  to Keep_Inputs
   set   Output_Enable_bar     to "0"
end vector

vector Output_Enable_false
   initialize  to Keep_Inputs
   set   Output_Enable_bar    to "1"
end vector

vector Write_Enable_true
   initialize  to Keep_Inputs
   set   Write_Enable_bar      to "0"
end vector

vector Write_Enable_false
   initialize  to Keep_Inputs
   drive Data_bus
   set   Data_bus             to "kk"
   set   Write_Enable_bar     to "1"
end vector

! Bidirectional Outputs

vector Receive_Data_00
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "00"
end vector

vector Receive_Data_01
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "01"
end vector

vector Receive_Data_03
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "03"
end vector

vector Receive_Data_07
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "07"
end vector

vector Receive_Data_0F
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "0F"
end vector

vector Receive_Data_1F
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "1F"
end vector

vector Receive_Data_3F
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "3F"
end vector

vector Receive_Data_7F
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "7F"
end vector

vector Receive_Data_FF
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "FF"
end vector

vector Receive_Data_FE
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "FE"
end vector

vector Receive_Data_FC
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "FC"
end vector

vector Receive_Data_F8
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "F8"
end vector

vector Receive_Data_F0
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "F0"
end vector

vector Receive_Data_E0
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "E0"
end vector

vector Receive_Data_C0
   initialize  to Keep_Inputs
   receive  Data_bus
   set   Data_bus              to "C0"
end vector

! Bidirectional Inputs

vector Drive_Data_00
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "00"
end vector

vector Drive_Data_01
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "01"
end vector

vector Drive_Data_03
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "03"
end vector

vector Drive_Data_07
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "07"
end vector

vector Drive_Data_0F
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "0F"
end vector

vector Drive_Data_1F
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "1F"
end vector

vector Drive_Data_3F
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "3F"
end vector

vector Drive_Data_7F
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "7F"
end vector

vector Drive_Data_FF
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "FF"
end vector

vector Drive_Data_FE
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "FE"
end vector

vector Drive_Data_FC
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "FC"
end vector

vector Drive_Data_F8
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "F8"
end vector

vector Drive_Data_F0
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "F0"
end vector

vector Drive_Data_E0
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "E0"
end vector

vector Drive_Data_C0
   initialize  to Keep_Inputs
   drive  Data_bus
   set   Data_bus              to "C0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector WEb_hi_D0
   initialize  to Keep_Inputs
   drive Data_D0
   set   Data_D0              to "k"
   set   Write_Enable_bar     to "1"
end vector

vector WEb_hi_D1
   initialize  to Keep_Inputs
   drive Data_D1
   set   Data_D1              to "k"
   set   Write_Enable_bar     to "1"
end vector

vector WEb_hi_D2
   initialize  to Keep_Inputs
   drive Data_D2
   set   Data_D2              to "k"
   set   Write_Enable_bar     to "1"
end vector

vector WEb_hi_D3
   initialize  to Keep_Inputs
   drive Data_D3
   set   Data_D3              to "k"
   set   Write_Enable_bar     to "1"
end vector

vector WEb_hi_D4
   initialize  to Keep_Inputs
   drive Data_D4
   set   Data_D4              to "k"
   set   Write_Enable_bar     to "1"
end vector

vector WEb_hi_D5
   initialize  to Keep_Inputs
   drive Data_D5
   set   Data_D5              to "k"
   set   Write_Enable_bar     to "1"
end vector

vector WEb_hi_D6
   initialize  to Keep_Inputs
   drive Data_D6
   set   Data_D6              to "k"
   set   Write_Enable_bar     to "1"
end vector

vector WEb_hi_D7
   initialize  to Keep_Inputs
   drive Data_D7
   set   Data_D7              to "k"
   set   Write_Enable_bar     to "1"
end vector

vector Receive_Data_D0_0
   initialize  to Keep_Inputs
   receive  Data_D0
   set   Data_D0               to "0"
end vector

vector Receive_Data_D0_1
   initialize  to Keep_Inputs
   receive  Data_D0
   set   Data_D0               to "1"
end vector

vector Receive_Data_D1_0
   initialize  to Keep_Inputs
   receive  Data_D1
   set   Data_D1               to "0"
end vector

vector Receive_Data_D1_1
   initialize  to Keep_Inputs
   receive  Data_D1
   set   Data_D1               to "1"
end vector

vector Receive_Data_D2_0
   initialize  to Keep_Inputs
   receive  Data_D2
   set   Data_D2               to "0"
end vector

vector Receive_Data_D2_1
   initialize  to Keep_Inputs
   receive  Data_D2
   set   Data_D2               to "1"
end vector

vector Receive_Data_D3_0
   initialize  to Keep_Inputs
   receive  Data_D3
   set   Data_D3               to "0"
end vector

vector Receive_Data_D3_1
   initialize  to Keep_Inputs
   receive  Data_D3
   set   Data_D3               to "1"
end vector

vector Receive_Data_D4_0
   initialize  to Keep_Inputs
   receive  Data_D4
   set   Data_D4               to "0"
end vector

vector Receive_Data_D4_1
   initialize  to Keep_Inputs
   receive  Data_D4
   set   Data_D4               to "1"
end vector

vector Receive_Data_D5_0
   initialize  to Keep_Inputs
   receive  Data_D5
   set   Data_D5               to "0"
end vector

vector Receive_Data_D5_1
   initialize  to Keep_Inputs
   receive  Data_D5
   set   Data_D5               to "1"
end vector

vector Receive_Data_D6_0
   initialize  to Keep_Inputs
   receive  Data_D6
   set   Data_D6               to "0"
end vector

vector Receive_Data_D6_1
   initialize  to Keep_Inputs
   receive  Data_D6
   set   Data_D6               to "1"
end vector

vector Receive_Data_D7_0
   initialize  to Keep_Inputs
   receive  Data_D7
   set   Data_D7               to "0"
end vector

vector Receive_Data_D7_1
   initialize  to Keep_Inputs
   receive  Data_D7
   set   Data_D7               to "1"
end vector

vector Drive_Data_D0_0
   initialize  to Keep_Inputs
   drive  Data_D0
   set   Data_D0               to "0"
end vector

vector Drive_Data_D0_1
   initialize  to Keep_Inputs
   drive  Data_D0
   set   Data_D0               to "1"
end vector

vector Drive_Data_D1_0
   initialize  to Keep_Inputs
   drive  Data_D1
   set   Data_D1               to "0"
end vector

vector Drive_Data_D1_1
   initialize  to Keep_Inputs
   drive  Data_D1
   set   Data_D1               to "1"
end vector

vector Drive_Data_D2_0
   initialize  to Keep_Inputs
   drive  Data_D2
   set   Data_D2               to "0"
end vector

vector Drive_Data_D2_1
   initialize  to Keep_Inputs
   drive  Data_D2
   set   Data_D2               to "1"
end vector

vector Drive_Data_D3_0
   initialize  to Keep_Inputs
   drive  Data_D3
   set   Data_D3               to "0"
end vector

vector Drive_Data_D3_1
   initialize  to Keep_Inputs
   drive  Data_D3
   set   Data_D3               to "1"
end vector

vector Drive_Data_D4_0
   initialize  to Keep_Inputs
   drive  Data_D4
   set   Data_D4               to "0"
end vector

vector Drive_Data_D4_1
   initialize  to Keep_Inputs
   drive  Data_D4
   set   Data_D4               to "1"
end vector

vector Drive_Data_D5_0
   initialize  to Keep_Inputs
   drive  Data_D5
   set   Data_D5               to "0"
end vector

vector Drive_Data_D5_1
   initialize  to Keep_Inputs
   drive  Data_D5
   set   Data_D5               to "1"
end vector

vector Drive_Data_D6_0
   initialize  to Keep_Inputs
   drive  Data_D6
   set   Data_D6               to "0"
end vector

vector Drive_Data_D6_1
   initialize  to Keep_Inputs
   drive  Data_D6
   set   Data_D6               to "1"
end vector

vector Drive_Data_D7_0
   initialize  to Keep_Inputs
   drive  Data_D7
   set   Data_D7               to "0"
end vector

vector Drive_Data_D7_1
   initialize  to Keep_Inputs
   drive  Data_D7
   set   Data_D7               to "1"
end vector


!***************************************************************
!***************************************************************

sub  Write (Address,Data)
   execute  Address
   execute  Chip_Selects_true
   execute  Write_Enable_true
   execute  Data
   execute  Write_Enable_false
end sub

sub   Read (Address,Data)
   execute  Address
   execute  Chip_Selects_true
   execute  Data
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Read). This reference can be modified in the
!AT call statement.

sub  Write_Dx (Address, Data_Dx, WEb_hi_Dx)
   execute  Address
   execute  Chip_Selects_true
   execute  Write_Enable_true
   execute  Data_Dx
   execute  WEb_hi_Dx
end sub

!****************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

   execute Initialize_Inputs
   call Write_Dx (Address_0000, Drive_Data_D0_0, WEb_hi_D0)
   call Read (Address_0000, Receive_Data_D0_0)

   call Write_Dx (Address_0000, Drive_Data_D0_1, WEb_hi_D0)
   call Read (Address_0000, Receive_Data_D0_1)

end unit

unit   "awaretest D1 Test"

   execute Initialize_Inputs
   call Write_Dx (Address_0000, Drive_Data_D1_0, WEb_hi_D1)
   call Read (Address_0000, Receive_Data_D1_0)

   call Write_Dx (Address_0000, Drive_Data_D1_1, WEb_hi_D1)
   call Read (Address_0000, Receive_Data_D1_1)

end unit

unit   "awaretest D2 Test"

   execute Initialize_Inputs
   call Write_Dx (Address_0000, Drive_Data_D2_0, WEb_hi_D2)
   call Read (Address_0000, Receive_Data_D2_0)

   call Write_Dx (Address_0000, Drive_Data_D2_1, WEb_hi_D2)
   call Read (Address_0000, Receive_Data_D2_1)

end unit

unit   "awaretest D3 Test"

   execute Initialize_Inputs
   call Write_Dx (Address_0000, Drive_Data_D3_0, WEb_hi_D3)
   call Read (Address_0000, Receive_Data_D3_0)

   call Write_Dx (Address_0000, Drive_Data_D3_1, WEb_hi_D3)
   call Read (Address_0000, Receive_Data_D3_1)

end unit

unit   "awaretest D4 Test"

   execute Initialize_Inputs
   call Write_Dx (Address_0000, Drive_Data_D4_0, WEb_hi_D4)
   call Read (Address_0000, Receive_Data_D4_0)

   call Write_Dx (Address_0000, Drive_Data_D4_1, WEb_hi_D4)
   call Read (Address_0000, Receive_Data_D4_1)

end unit

unit   "awaretest D5 Test"

   execute Initialize_Inputs
   call Write_Dx (Address_0000, Drive_Data_D5_0, WEb_hi_D5)
   call Read (Address_0000, Receive_Data_D5_0)

   call Write_Dx (Address_0000, Drive_Data_D5_1, WEb_hi_D5)
   call Read (Address_0000, Receive_Data_D5_1)

end unit

unit   "awaretest D6 Test"

   execute Initialize_Inputs
   call Write_Dx (Address_0000, Drive_Data_D6_0, WEb_hi_D6)
   call Read (Address_0000, Receive_Data_D6_0)

   call Write_Dx (Address_0000, Drive_Data_D6_1, WEb_hi_D6)
   call Read (Address_0000, Receive_Data_D6_1)

end unit

unit   "awaretest D7 Test"

   execute Initialize_Inputs
   call Write_Dx (Address_0000, Drive_Data_D7_0, WEb_hi_D7)
   call Read (Address_0000, Receive_Data_D7_0)

   call Write_Dx (Address_0000, Drive_Data_D7_1, WEb_hi_D7)
   call Read (Address_0000, Receive_Data_D7_1)

end unit

unit  "RAM Test"
   execute Initialize_Inputs
   call Write (Address_0000,Drive_Data_01)
   call Write (Address_0001,Drive_Data_03)
   call Write (Address_0003,Drive_Data_07)
   call Write (Address_0007,Drive_Data_0F)
   call Write (Address_000F,Drive_Data_1F)
   call Write (Address_001F,Drive_Data_3F)
   call Write (Address_003F,Drive_Data_7F)
   call Write (Address_007F,Drive_Data_FF)
   call Write (Address_00FF,Drive_Data_FE)
   call Write (Address_01FF,Drive_Data_FC)
   call Write (Address_03FF,Drive_Data_F8)
   call Write (Address_07FF,Drive_Data_F0)
   call Write (Address_0FFF,Drive_Data_E0)
   call Write (Address_1FFF,Drive_Data_C0)

   call Read (Address_0000,Receive_Data_01)
   call Read (Address_0001,Receive_Data_03)
   call Read (Address_0003,Receive_Data_07)
   call Read (Address_0007,Receive_Data_0F)
   call Read (Address_000F,Receive_Data_1F)
   call Read (Address_001F,Receive_Data_3F)
   call Read (Address_003F,Receive_Data_7F)
   call Read (Address_007F,Receive_Data_FF)
   call Read (Address_00FF,Receive_Data_FE)
   call Read (Address_01FF,Receive_Data_FC)
   call Read (Address_03FF,Receive_Data_F8)
   call Read (Address_07FF,Receive_Data_F0)
   call Read (Address_0FFF,Receive_Data_E0)
   call Read (Address_1FFF,Receive_Data_C0)

end unit

unit  "Test Chip_Selects false"
   execute Initialize_Inputs
   call Write (Address_0000,Drive_Data_00)
   execute  Address_0000
   execute  Chip_Selects_false
   execute  Write_Enable_true
   execute  Drive_Data_FF
   execute  Write_Enable_false
   call Read (Address_0000,Receive_Data_00)
end unit

unit  "Test Chip_Select1 false"
   execute Initialize_Inputs
   call Write (Address_0000,Drive_Data_00)
   execute  Address_0000
   execute  Chip_Select1_false
   execute  Write_Enable_true
   execute  Drive_Data_FF
   execute  Write_Enable_false
   call Read (Address_0000,Receive_Data_00)
end unit

unit  "Test Chip_Select2 false"
   execute Initialize_Inputs
   call Write (Address_0000,Drive_Data_00)
   execute  Address_0000
   execute  Chip_Select2_false
   execute  Write_Enable_true
   execute  Drive_Data_FF
   execute  Write_Enable_false
   call Read (Address_0000,Receive_Data_00)
end unit


unit  "Test Write_bar false"
   execute Initialize_Inputs
   call Write (Address_0000,Drive_Data_00)
   execute  Address_0000
   execute  Chip_Selects_true
   execute  Write_Enable_false
   execute  Drive_Data_FF
   execute  Write_Enable_false
   execute  Chip_Selects_false
   call Read (Address_0000,Receive_Data_00)
end unit

unit  "Test Output_Enable_bar false"
   execute Initialize_Inputs
   call Write (Address_0000,Drive_Data_00)
   execute  Address_0000
   execute  Chip_Selects_true
   execute  Output_Enable_false
   execute  Receive_Data_FF
   execute  Chip_Selects_false
   execute  Output_Enable_true
   call Read (Address_0000,Receive_Data_00)
end unit

!End of test