!!!!    6    0    1  987038709  V47e6                                         

! Device           : 14599
! Function         : 8-bit Addressable Latch
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 1u
receive delay 900n

assign VDD           to pins 18
assign VSS           to pins  9

assign Chip_Enable   to pins 8
assign Data          to pins 3
assign Write_Disable to pins 4
assign Write_Read_bar to pins 10
assign Reset         to pins 2
assign Address       to pins 7,6,5
assign Data_Outputs  to pins 1,17,16,15,14,13,12,11
assign Data_D0       to pins 11             !AT Added for minimum pin test.
assign Data_D1       to pins 12             !AT Added for minimum pin test.
assign Data_D2       to pins 13             !AT Added for minimum pin test.
assign Data_D3       to pins 14             !AT Added for minimum pin test.
assign Data_D4       to pins 15             !AT Added for minimum pin test.
assign Data_D5       to pins 16             !AT Added for minimum pin test.
assign Data_D6       to pins 17             !AT Added for minimum pin test.
assign Data_D7       to pins 1              !AT Added for minimum pin test.

power  VDD, VSS
family  CMOS

inputs Write_Disable, Reset
inputs Address, Write_Read_bar, Chip_enable

outputs Data_Outputs
outputs Data_D0, Data_D1, Data_D2, Data_D3  !AT Added for minimum pin test.
outputs Data_D4, Data_D5, Data_D6, Data_D7  !AT Added for minimum pin test.

bidirectional Data

disable Data with Write_Read_bar to "1"

when  Write_Read_bar is "1" inputs   Data
when  Write_Read_bar is "0" outputs  Data

trace  Data_Outputs  to  Write_Disable, Reset ,Data
trace  Data_Outputs  to  Address, Write_Read_bar, Chip_enable
trace  Data          to  Write_Disable, Reset
trace  Data          to  Address, Write_Read_bar, Chip_enable


!***********************************************************************
!***********************************************************************

vector Address_000
     set Reset       to "0"
     set Address     to "000"
     set Chip_Enable    to  "k"
end vector

vector Address_001
     set Reset       to "0"
     set Address     to "001"
     set Chip_Enable    to  "k"
end vector

vector Address_010
     set Reset       to "0"
     set Address     to "010"
     set Chip_Enable    to  "k"
end vector

vector Address_011
     set Reset       to "0"
     set Address     to "011"
     set Chip_Enable    to  "k"
end vector

vector Address_100
     set Reset       to "0"
     set Address     to "100"
     set Chip_Enable    to  "k"
end vector

vector Address_101
     set Reset       to "0"
     set Address     to "101"
     set Chip_Enable    to  "k"
end vector

vector Address_110
     set Reset       to "0"
     set Address     to "110"
     set Chip_Enable    to  "k"
end vector

vector Address_111
     set Reset       to "0"
     set Address     to "111"
     set Chip_Enable    to  "k"
end vector

vector  Enable_Writing
     set Reset       to "0"
     set Address     to "KKK"
     set Write_Disable  to  "0"
     set Chip_Enable    to  "k"
end vector

vector  Write_Data_0
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Data        to "0"
     set Write_Disable  to "K"
     set Write_Read_bar to "1"
     set Chip_Enable    to  "k"
end vector

vector  Write_Data_1
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Data        to "1"
     set Write_Disable  to "K"
     set Write_Read_bar to "1"
     set Chip_Enable    to  "k"
end vector

vector  Read_Data_0
     receive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Data        to "0"
     set Write_Disable  to "K"
     set Write_Read_bar to "0"
     set Chip_Enable    to  "k"
end vector

vector  Read_Data_1
     receive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Data        to "1"
     set Write_Disable  to "K"
     set Write_Read_bar to "0"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XXXXXXX0
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XXXXXXX0"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XXXXXXX1
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XXXXXXX1"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XXXXXX0X
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XXXXXX0X"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XXXXXX1X
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XXXXXX1X"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XXXXX0XX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XXXXX0XX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XXXXX1XX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XXXXX1XX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XXXX0XXX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XXXX0XXX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XXXX1XXX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XXXX1XXX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XXX0XXXX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XXX0XXXX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XXX1XXXX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XXX1XXXX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XX0XXXXX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XX0XXXXX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_XX1XXXXX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "XX1XXXXX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_X0XXXXXX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "X0XXXXXX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_X1XXXXXX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "X1XXXXXX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_0XXXXXXX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "0XXXXXXX"
     set Chip_Enable    to  "k"
end vector

vector  Data_Output_1XXXXXXX
     drive Data
     set Reset       to "K"
     set Address     to "KKK"
     set Write_Disable  to "K"
     set Data        to "K"
     set Data_Outputs  to "1XXXXXXX"
     set Chip_Enable    to  "k"
end vector

vector  Latch_Data
     drive Data
     set Address     to "KKK"
     set Data        to "K"
     set Reset       to "K"
     set Write_Disable  to "1"
     set Chip_Enable    to  "k"
end vector

vector  Reset_Device
     set Reset       to "1"
     set Write_Disable  to "1"
     set Data_Outputs  to "00000000"
     set Chip_Enable    to  "k"
end vector

vector  Enable
     set Chip_Enable    to  "1"
end vector

vector  Disable
     set Chip_Enable    to  "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  Data_Output_D0_0
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D0        to "0"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D0_1
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D0        to "1"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D1_0
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D1        to "0"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D1_1
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D1        to "1"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D2_0
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D2        to "0"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D2_1
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D2        to "1"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D3_0
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D3        to "0"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D3_1
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D3        to "1"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D4_0
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D4        to "0"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D4_1
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D4        to "1"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D5_0
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D5        to "0"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D5_1
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D5        to "1"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D6_0
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D6        to "0"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D6_1
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D6        to "1"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D7_0
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D7        to "0"
     set Chip_Enable    to "k"
end vector

vector  Data_Output_D7_1
     drive Data
     set Reset          to "K"
     set Address        to "KKK"
     set Write_Disable  to "K"
     set Data           to "K"
     set Data_D7        to "1"
     set Chip_Enable    to "k"
end vector

vector  Reset_Device_Dx
     set Reset       to "1"
     set Write_Disable  to "1"
     set Chip_Enable    to  "k"
end vector

!***********************************************************************
!***********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"
     execute Enable
     execute Address_000
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_D0_0
     execute Write_Data_1
     execute Data_Output_D0_1
     execute Reset_Device_Dx
end unit

unit   "awaretest D1 Test"
     execute Enable
     execute Address_001
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_D1_0
     execute Write_Data_1
     execute Data_Output_D1_1
     execute Reset_Device_Dx
end unit

unit   "awaretest D2 Test"
     execute Enable
     execute Address_010
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_D2_0
     execute Write_Data_1
     execute Data_Output_D2_1
     execute Reset_Device_Dx
end unit

unit   "awaretest D3 Test"
     execute Enable
     execute Address_011
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_D3_0
     execute Write_Data_1
     execute Data_Output_D3_1
     execute Reset_Device_Dx
end unit

unit   "awaretest D4 Test"
     execute Enable
     execute Address_100
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_D4_0
     execute Write_Data_1
     execute Data_Output_D4_1
     execute Reset_Device_Dx
end unit

unit   "awaretest D5 Test"
     execute Enable
     execute Address_101
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_D5_0
     execute Write_Data_1
     execute Data_Output_D5_1
     execute Reset_Device_Dx
end unit

unit   "awaretest D6 Test"
     execute Enable
     execute Address_110
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_D6_0
     execute Write_Data_1
     execute Data_Output_D6_1
     execute Reset_Device_Dx
end unit

unit   "awaretest D7 Test"
     execute Enable
     execute Address_111
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_D7_0
     execute Write_Data_1
     execute Data_Output_D7_1
     execute Reset_Device_Dx
end unit

unit "Latch 0 test"
     execute Enable
     execute Address_000
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_XXXXXXX0
     execute Read_Data_0
     execute Write_Data_1
     execute Data_Output_XXXXXXX1
     execute Read_Data_1
     execute Latch_Data
     execute Write_Data_0
     execute Data_Output_XXXXXXX1
     execute Reset_Device
end unit

unit "Latch 1 test"
     execute Enable
     execute Address_001
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_XXXXXX0X
     execute Read_Data_0
     execute Write_Data_1
     execute Data_Output_XXXXXX1X
     execute Read_Data_1
     execute Latch_Data
     execute Write_Data_0
     execute Data_Output_XXXXXX1X
     execute Reset_Device
end unit

unit "Latch 2 test"
     execute Enable
     execute Address_010
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_XXXXX0XX
     execute Read_Data_0
     execute Write_Data_1
     execute Data_Output_XXXXX1XX
     execute Read_Data_1
     execute Latch_Data
     execute Write_Data_0
     execute Data_Output_XXXXX1XX
     execute Reset_Device
end unit

unit "Latch 3 test"
     execute Enable
     execute Address_011
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_XXXX0XXX
     execute Read_Data_0
     execute Write_Data_1
     execute Data_Output_XXXX1XXX
     execute Read_Data_1
     execute Latch_Data
     execute Write_Data_0
     execute Data_Output_XXXX1XXX
     execute Reset_Device
end unit

unit "Latch 4 test"
     execute Enable
     execute Address_100
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_XXX0XXXX
     execute Read_Data_0
     execute Write_Data_1
     execute Data_Output_XXX1XXXX
     execute Read_Data_1
     execute Latch_Data
     execute Write_Data_0
     execute Data_Output_XXX1XXXX
     execute Reset_Device
end unit

unit "Latch 5 test"
     execute Enable
     execute Address_101
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_XX0XXXXX
     execute Read_Data_0
     execute Write_Data_1
     execute Data_Output_XX1XXXXX
     execute Read_Data_1
     execute Latch_Data
     execute Write_Data_0
     execute Data_Output_XX1XXXXX
     execute Reset_Device
end unit

unit "Latch 6 test"
     execute Enable
     execute Address_110
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_X0XXXXXX
     execute Read_Data_0
     execute Write_Data_1
     execute Data_Output_X1XXXXXX
     execute Read_Data_1
     execute Latch_Data
     execute Write_Data_0
     execute Data_Output_X1XXXXXX
     execute Reset_Device
end unit

unit "Latch 7 test"
     execute Enable
     execute Address_111
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_0XXXXXXX
     execute Read_Data_0
     execute Write_Data_1
     execute Data_Output_1XXXXXXX
     execute Read_Data_1
     execute Latch_Data
     execute Write_Data_0
     execute Data_Output_1XXXXXXX
     execute Reset_Device
end unit

unit "Enable test using latch 1"
     execute Disable
     execute Address_000
     execute Enable_Writing
     execute Write_Data_0
     execute Data_Output_XXXXXXX0
     execute Write_Data_1

     execute Data_Output_XXXXXXX0
end unit

!    End of test