!!!!    6    0    1  987182821  V47ce                                         

! Device           : idt7140a
! Function         : 1kx8 dual-port RAM
! revision         : B.01.00
! safeguard        : high_out_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

!IDT: High Performance CMOS Data Book, 1986

sequential

!*****************48 pin DIP, PLCC, and QFP**************************

assign VCC                    to pins 48
assign GND                    to pins 24

assign CE_bar_left            to pins 1
assign RW_bar_left            to pins 2
assign OE_bar_left            to pins 5
assign Add_left               to pins 15,14,13,12,11
assign Add_left               to pins 10,9,8,7,6

assign BUSY_bar_left          to pins 3
assign INT_bar_left           to pins 4

assign IO_port_left           to pins 23,22,21,20
assign IO_port_left           to pins 19,18,17,16
assign IO_port_left_D0        to pins 16   !AT Added for minimum pin test.
assign IO_port_left_D1        to pins 17   !AT Added for minimum pin test.
assign IO_port_left_D2        to pins 18   !AT Added for minimum pin test.
assign IO_port_left_D3        to pins 19   !AT Added for minimum pin test.
assign IO_port_left_D4        to pins 20   !AT Added for minimum pin test.
assign IO_port_left_D5        to pins 21   !AT Added for minimum pin test.
assign IO_port_left_D6        to pins 22   !AT Added for minimum pin test.
assign IO_port_left_D7        to pins 23   !AT Added for minimum pin test.

assign Disable_pins_left      to pins 1,5,2

assign CE_bar_right           to pins 47
assign RW_bar_right           to pins 46
assign OE_bar_right           to pins 43
assign Add_right              to pins 33,34,35,36,37
assign Add_right              to pins 38,39,40,41,42

assign BUSY_bar_right         to pins 45
assign INT_bar_right          to pins 44

assign IO_port_right          to pins 32,31,30,29
assign IO_port_right          to pins 28,27,26,25
assign IO_port_right_D0       to pins 25   !AT Added for minimum pin test.
assign IO_port_right_D1       to pins 26   !AT Added for minimum pin test.
assign IO_port_right_D2       to pins 27   !AT Added for minimum pin test.
assign IO_port_right_D3       to pins 28   !AT Added for minimum pin test.
assign IO_port_right_D4       to pins 29   !AT Added for minimum pin test.
assign IO_port_right_D5       to pins 30   !AT Added for minimum pin test.
assign IO_port_right_D6       to pins 31   !AT Added for minimum pin test.
assign IO_port_right_D7       to pins 32   !AT Added for minimum pin test.

assign Disable_pins_right     to pins 47,43,46

!***************52 pin PLCC and QFP**********************************
!
!assign GND            to pins 24
!
!assign CE_bar_left            to pins 1
!assign RW_bar_left            to pins 2
!assign OE_bar_left            to pins 6
!assign Add_left               to pins 16,15,14,13,12
!assign Add_left               to pins 11,10,9,8,7
!
!assign BUSY_bar_left          to pins 3
!assign INT_bar_left           to pins 4
!
!assign IO_port_left           to pins 24,23,22,21
!assign IO_port_left           to pins 20,19,18,17
!assign IO_port_left_D0        to pins 17   !AT Added for minimum pin test.
!assign IO_port_left_D1        to pins 18   !AT Added for minimum pin test.
!assign IO_port_left_D2        to pins 19   !AT Added for minimum pin test.
!assign IO_port_left_D3        to pins 20   !AT Added for minimum pin test.
!assign IO_port_left_D4        to pins 21   !AT Added for minimum pin test.
!assign IO_port_left_D5        to pins 22   !AT Added for minimum pin test.
!assign IO_port_left_D6        to pins 23   !AT Added for minimum pin test.
!assign IO_port_left_D7        to pins 24   !AT Added for minimum pin test.
!
!assign Disable_pins_left      to pins 1,6,2
!
!assign CE_bar_right           to pins 51
!assign RW_bar_right           to pins 50
!assign OE_bar_right           to pins 46
!assign Add_right              to pins 36,37,38,39,40
!assign Add_right              to pins 41,42,43,44,45
!
!assign BUSY_bar_right         to pins 49
!assign INT_bar_right          to pins 48
!
!assign IO_port_right          to pins 34,33,32,31
!assign IO_port_right          to pins 30,29,28,27
!assign IO_port_right_D0       to pins 27   !AT Added for minimum pin test.
!assign IO_port_right_D1       to pins 28   !AT Added for minimum pin test.
!assign IO_port_right_D2       to pins 29   !AT Added for minimum pin test.
!assign IO_port_right_D3       to pins 30   !AT Added for minimum pin test.
!assign IO_port_right_D4       to pins 31   !AT Added for minimum pin test.
!assign IO_port_right_D5       to pins 32   !AT Added for minimum pin test.
!assign IO_port_right_D6       to pins 33   !AT Added for minimum pin test.
!assign IO_port_right_D7       to pins 34   !AT Added for minimum pin test.
!
!assign Disable_pins_right     to pins 51,46,50
!
!assign NC                     to pins 5,25,35,47
!
!nondigital NC
!*********************************************************************

inputs RW_bar_left
inputs OE_bar_left,Add_left
inputs RW_bar_right
inputs OE_bar_right,Add_right
inputs BUSY_bar_left,BUSY_bar_right

outputs INT_bar_left,INT_bar_right

bidirectional IO_port_left, IO_port_right,CE_bar_left,CE_bar_right
bidirectional IO_port_right_D0, IO_port_right_D1 !AT Added for min. pin test.
bidirectional IO_port_right_D2, IO_port_right_D3 !AT Added for min. pin test.
bidirectional IO_port_right_D4, IO_port_right_D5 !AT Added for min. pin test.
bidirectional IO_port_right_D6, IO_port_right_D7 !AT Added for min. pin test.
bidirectional IO_port_left_D0, IO_port_left_D1   !AT Added for min. pin test.
bidirectional IO_port_left_D2, IO_port_left_D3   !AT Added for min. pin test.
bidirectional IO_port_left_D4, IO_port_left_D5   !AT Added for min. pin test.
bidirectional IO_port_left_D6, IO_port_left_D7   !AT Added for min. pin test.

format hexadecimal IO_port_left,IO_port_right

family  TTL
power   VCC,GND

!*************      Backtrace Information  ***************************

trace IO_port_left to CE_bar_left,OE_bar_left,RW_bar_left,Add_left
trace IO_port_left to BUSY_bar_left,IO_port_right,RW_bar_right
trace IO_port_left to CE_bar_right,Add_right
trace INT_bar_left to Add_right,RW_bar_right,IO_port_right

trace IO_port_right to CE_bar_right,OE_bar_right,RW_bar_right,Add_right
trace IO_port_right to BUSY_bar_right,IO_port_left,RW_bar_left
trace IO_port_right to CE_bar_left,Add_left
trace INT_bar_right to Add_right,RW_bar_right,IO_port_left

!************     Disable information   ******************************

disable IO_port_left with Disable_pins_left to "1XX"
disable IO_port_left with Disable_pins_left to "011"
disable CE_bar_left with Disable_pins_left to "1XX"
disable CE_bar_left with Disable_pins_left to "011"

disable IO_port_right with Disable_pins_right to "1XX"
disable IO_port_right with Disable_pins_right to "011"
disable CE_bar_right with Disable_pins_right to "1XX"
disable CE_bar_right with Disable_pins_right to "011"


when Disable_pins_left is "0X0" inputs IO_port_left
when Disable_pins_left is "001" outputs IO_port_left
when Disable_pins_left is "1XX" inactive IO_port_left
when Disable_pins_left is "011" inactive IO_port_left

when Disable_pins_right is "0X0" inputs IO_port_right
when Disable_pins_right is "001" outputs IO_port_right
when Disable_pins_right is "1XX" inactive IO_port_right
when Disable_pins_right is "011" inactive IO_port_right

warning "Pull-ups are required on the IO_port_right and IO_port_left pins."
warning "Pull-ups are required on the CE_bar_right and CE_bar_left pins."
warning "Pull-ups are required on the open drain outputs,"
warning "INT_bar_right, and INT_bar_left for the test to run."

warning "Precise power settings required:"
! This device will pass reliably with    4.5v < VCC < 5.0v . This
! is in contrast with the data sheets claiming reliability up to 5.5v .

!**********************************************************************
!***********************   VECTOR   SECTION    ************************
!**********************************************************************

vector Set_values_left
   drive CE_bar_left
   set BUSY_bar_left   to "1"
   set OE_bar_left     to "0"
   set CE_bar_left     to "0"
   set RW_bar_left     to "1"
   set Add_left        to "0000000000"
end vector

vector Set_values_right
   drive CE_bar_right
   set BUSY_bar_right  to "1"
   set OE_bar_right    to "0"
   set CE_bar_right    to "0"
   set RW_bar_right    to "1"
   set Add_right       to "0000000000"
end vector

vector Set_values_both
   drive CE_bar_right
   drive CE_bar_left
   set BUSY_bar_right  to "1"
   set BUSY_bar_left   to "1"
   set CE_bar_right    to "0"
   set CE_bar_left     to "0"
   set RW_bar_left     to "1"
   set RW_bar_right    to "1"
   set OE_bar_left     to "0"
   set OE_bar_right    to "0"
   set Add_right       to "0000000000"
   set Add_left        to "0000000000"
end vector

vector Keep_values_left
   drive CE_bar_left
   set BUSY_bar_left   to "k"
   set OE_bar_left     to "k"
   set CE_bar_left     to "k"
   set RW_bar_left     to "k"
   set Add_left        to "kkkkkkkkkk"
end vector

vector Keep_values_right
   drive CE_bar_right
   set BUSY_bar_Right  to "k"
   set OE_bar_right    to "k"
   set CE_bar_right    to "k"
   set RW_bar_right    to "k"
   set Add_right       to "kkkkkkkkkk"
end vector

vector Keep_values_both
   drive CE_bar_right
   drive CE_bar_left
   set BUSY_bar_right  to "k"
   set BUSY_bar_left   to "k"
   set CE_bar_right    to "k"
   set CE_bar_left     to "k"
   set RW_bar_left     to "k"
   set RW_bar_right    to "k"
   set OE_bar_left     to "k"
   set OE_bar_right    to "k"
   set Add_right       to "kkkkkkkkkk"
   set Add_left        to "kkkkkkkkkk"
end vector

vector CE_bar_left_low
   initialize to Keep_values_left
   set CE_bar_left     to "0"
end vector

vector CE_bar_right_low
   initialize to Keep_values_right
   set CE_bar_right    to "0"
end vector

vector CE_bar_left_hi
   initialize to Keep_values_left
   set CE_bar_left     to "1"
end vector

vector CE_bar_right_hi
   initialize to Keep_values_right
   set CE_bar_right    to "1"
end vector

vector OE_bar_left_low
   initialize to Keep_values_left
   set OE_bar_left     to "0"
end vector

vector OE_bar_right_low
   initialize to Keep_values_right
   set OE_bar_right    to "0"
end vector

vector OE_bar_left_hi
   initialize to Keep_values_left
   set OE_bar_left     to "1"
end vector

vector OE_bar_right_hi
   initialize to Keep_values_right
   set OE_bar_right    to "1"
end vector

vector RW_bar_left_low
   initialize to Keep_values_left
   set RW_bar_left     to "0"
end vector

vector RW_bar_right_low
   initialize to Keep_values_right
   set RW_bar_right    to "0"
end vector

vector RW_bar_left_hi
   initialize to Keep_values_left
   set RW_bar_left     to "1"
end vector

vector RW_bar_right_hi
   initialize to Keep_values_right
   set RW_bar_right    to "1"
end vector

vector RW_bar_left_low_B
   initialize to Keep_values_both
   set RW_bar_left     to "0"
end vector

vector RW_bar_right_low_B
   initialize to Keep_values_both
   set RW_bar_right    to "0"
end vector

vector RW_bar_left_hi_B
   initialize to Keep_values_both
   set RW_bar_left     to "1"
end vector

vector RW_bar_right_hi_B
   initialize to Keep_values_both
   set RW_bar_right    to "1"
end vector

vector BUSY_bar_left_low
   initialize to Keep_values_left
   set BUSY_bar_left   to "0"
end vector

vector BUSY_bar_right_low
   initialize to Keep_values_right
   set BUSY_bar_right  to "0"
end vector

vector BUSY_bar_left_hi
   initialize to Keep_values_left
   set BUSY_bar_left   to "1"
end vector

vector BUSY_bar_right_hi
   initialize to Keep_values_right
   set BUSY_bar_right  to "1"
end vector

vector INT_bar_left_low
   initialize to Keep_values_both
   set INT_bar_left    to "0"
end vector

vector INT_bar_right_low
   initialize to Keep_values_both
   set INT_bar_right   to "0"
end vector

vector INT_bar_left_hi
   initialize to Keep_values_both
   set INT_bar_left    to "1"
end vector

vector INT_bar_right_hi
   initialize to Keep_values_both
   set INT_bar_right   to "1"
end vector

vector INT_bar_left_low_Setup
   initialize to Keep_values_both
   set Add_right     to "1111111110"
   set RW_bar_right  to "0"
end vector

vector INT_bar_right_low_Setup
   initialize to Keep_values_both
   set Add_left      to "1111111111"
   set RW_bar_left   to "0"
end vector

vector INT_bar_left_hi_Setup
   initialize to Keep_values_both
   set Add_left      to "1111111110"
   set OE_bar_left   to "0"
end vector

vector INT_bar_right_hi_Setup
   initialize to Keep_values_both
   set Add_right     to "1111111111"
   set OE_bar_right  to "0"
end vector

!**********************************************************************

vector Add_left_0000000000
   initialize to Keep_values_left
   set Add_left      to "0000000000"
end vector

vector Add_left_0000000000_B
   initialize to Keep_values_both
   set Add_left      to "0000000000"
end vector

vector Add_left_0000000001
   initialize to Keep_values_left
   set Add_left      to "0000000001"
end vector

vector Add_left_0000000001_B
   initialize to Keep_values_both
   set Add_left      to "0000000001"
end vector

vector Add_left_0000000010
   initialize to Keep_values_left
   set Add_left      to "0000000010"
end vector

vector Add_left_0000000100
   initialize to Keep_values_left
   set Add_left      to "0000000100"
end vector

vector Add_left_0000001000
   initialize to Keep_values_left
   set Add_left      to "0000001000"
end vector

vector Add_left_0000010000
   initialize to Keep_values_left
   set Add_left      to "0000010000"
end vector

vector Add_left_0000100000
   initialize to Keep_values_left
   set Add_left      to "0000100000"
end vector

vector Add_left_0001000000
   initialize to Keep_values_left
   set Add_left      to "0001000000"
end vector

vector Add_left_0010000000
   initialize to Keep_values_left
   set Add_left      to "0010000000"
end vector

vector Add_left_0100000000
   initialize to Keep_values_left
   set Add_left      to "0100000000"
end vector

vector Add_left_1000000000
   initialize to Keep_values_left
   set Add_left      to "1000000000"
end vector

vector Add_left_1111111110
   initialize to Keep_values_both
   set Add_left      to "1111111110"
end vector

vector Add_left_1111111111
   initialize to Keep_values_both
   set Add_left      to "1111111111"
end vector

vector Add_right_0000000000_B
   initialize to Keep_values_both
   set Add_right     to "0000000000"
end vector

vector Add_right_0000000000
   initialize to Keep_values_right
   set Add_right     to "0000000000"
end vector

vector Add_right_0000000001_B
   initialize to Keep_values_both
   set Add_right     to "0000000001"
end vector

vector Add_right_0000000001
   initialize to Keep_values_right
   set Add_right     to "0000000001"
end vector

vector Add_right_0000000010
   initialize to Keep_values_right
   set Add_right     to "0000000010"
end vector

vector Add_right_0000000100
   initialize to Keep_values_right
   set Add_right     to "0000000100"
end vector

vector Add_right_0000001000
   initialize to Keep_values_right
   set Add_right     to "0000001000"
end vector

vector Add_right_0000010000
   initialize to Keep_values_right
   set Add_right     to "0000010000"
end vector

vector Add_right_0000100000
   initialize to Keep_values_right
   set Add_right     to "0000100000"
end vector

vector Add_right_0001000000
   initialize to Keep_values_right
   set Add_right     to "0001000000"
end vector

vector Add_right_0010000000
   initialize to Keep_values_right
   set Add_right     to "0010000000"
end vector

vector Add_right_0100000000
   initialize to Keep_values_right
   set Add_right     to "0100000000"
end vector

vector Add_right_1000000000
   initialize to Keep_values_right
   set Add_right     to "1000000000"
end vector

vector Add_right_1111111110
   initialize to Keep_values_both
   set Add_right     to "1111111110"
end vector

vector Add_right_1111111111
   initialize to Keep_values_both
   set Add_right     to "1111111111"
end vector

!**********************************************************************

vector Dat_left_00_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "00"
end vector

vector Dat_left_00_W_B
   initialize to Keep_values_both
   drive IO_port_left
   set IO_port_left  to "00"
end vector

vector Dat_left_01_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "01"
end vector

vector Dat_left_01_W_B
   initialize to Keep_values_both
   drive IO_port_left
   set IO_port_left  to "01"
end vector

vector Dat_left_02_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "02"
end vector

vector Dat_left_04_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "04"
end vector

vector Dat_left_08_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "08"
end vector

vector Dat_left_10_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "10"
end vector

vector Dat_left_20_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "20"
end vector

vector Dat_left_40_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "40"
end vector

vector Dat_left_80_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "80"
end vector

vector Dat_left_81_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "81"
end vector

vector Dat_left_82_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "82"
end vector

vector Dat_left_0F_W
   initialize to Keep_values_both
   drive IO_port_left
   set IO_port_left  to "0F"
end vector

vector Dat_left_FF_W
   initialize to Keep_values_left
   drive IO_port_left
   set IO_port_left  to "FF"
end vector

vector Dat_right_00_W_B
   initialize to Keep_values_both
   drive IO_port_right
   set IO_port_right to "00"
end vector

vector Dat_right_00_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "00"
end vector

vector Dat_right_01_W_B
   initialize to Keep_values_both
   drive IO_port_right
   set IO_port_right to "01"
end vector

vector Dat_right_01_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "01"
end vector

vector Dat_right_02_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "02"
end vector

vector Dat_right_04_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "04"
end vector

vector Dat_right_08_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "08"
end vector

vector Dat_right_10_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "10"
end vector

vector Dat_right_20_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "20"
end vector

vector Dat_right_40_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "40"
end vector

vector Dat_right_80_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "80"
end vector

vector Dat_right_81_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "81"
end vector

vector Dat_right_82_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "82"
end vector

vector Dat_right_0F_W
   initialize to Keep_values_both
   drive IO_port_right
   set IO_port_right to "0F"
end vector

vector Dat_right_FF_W
   initialize to Keep_values_right
   drive IO_port_right
   set IO_port_right to "FF"
end vector

vector Dat_left_00_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "00"
end vector

vector Dat_left_00_R_B
   initialize to Keep_values_both
   receive IO_port_left
   set IO_port_left  to "00"
end vector

vector Dat_left_01_R_B
   initialize to Keep_values_both
   receive IO_port_left
   set IO_port_left  to "01"
end vector

vector Dat_left_01_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "01"
end vector

vector Dat_left_02_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "02"
end vector

vector Dat_left_04_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "04"
end vector

vector Dat_left_08_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "08"
end vector

vector Dat_left_10_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "10"
end vector

vector Dat_left_20_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "20"
end vector

vector Dat_left_40_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "40"
end vector

vector Dat_left_80_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "80"
end vector

vector Dat_left_81_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "81"
end vector

vector Dat_left_82_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "82"
end vector

vector Dat_left_FF_R
   initialize to Keep_values_left
   receive IO_port_left
   set IO_port_left  to "FF"
end vector

vector Dat_left_xx_R
   initialize to Keep_values_both
   receive IO_port_left
   set IO_port_left  to "xx"
end vector

vector Dat_right_00_R_B
   initialize to Keep_values_both
   receive IO_port_right
   set IO_port_right to "00"
end vector

vector Dat_right_00_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "00"
end vector

vector Dat_right_01_R_B
   initialize to Keep_values_both
   receive IO_port_right
   set IO_port_right to "01"
end vector

vector Dat_right_01_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "01"
end vector

vector Dat_right_02_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "02"
end vector

vector Dat_right_04_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "04"
end vector

vector Dat_right_08_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "08"
end vector

vector Dat_right_10_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "10"
end vector

vector Dat_right_20_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "20"
end vector

vector Dat_right_40_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "40"
end vector

vector Dat_right_80_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "80"
end vector

vector Dat_right_81_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "81"
end vector

vector Dat_right_82_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "82"
end vector

vector Dat_right_FF_R
   initialize to Keep_values_right
   receive IO_port_right
   set IO_port_right to "FF"
end vector

vector Dat_right_xx_R
   initialize to Keep_values_both
   receive IO_port_right
   set IO_port_right to "xx"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector Dat_left_D0_0_W
   initialize to Keep_values_left
   drive IO_port_left_D0
   set IO_port_left_D0     to "0"
end vector

vector Dat_left_D0_1_W
   initialize to Keep_values_left
   drive IO_port_left_D0
   set IO_port_left_D0     to "1"
end vector

vector Dat_right_D0_0_W
   initialize to Keep_values_right
   drive IO_port_right_D0
   set IO_port_right_D0    to "0"
end vector

vector Dat_right_D0_1_W
   initialize to Keep_values_right
   drive IO_port_right_D0
   set IO_port_right_D0    to "1"
end vector

vector Dat_left_D0_0_R
   initialize to Keep_values_left
   receive IO_port_left_D0
   set IO_port_left_D0     to "0"
end vector

vector Dat_left_D0_1_R
   initialize to Keep_values_left
   receive IO_port_left_D0
   set IO_port_left_D0     to "1"
end vector

vector Dat_right_D0_0_R
   initialize to Keep_values_right
   receive IO_port_right_D0
   set IO_port_right_D0    to "0"
end vector

vector Dat_right_D0_1_R
   initialize to Keep_values_right
   receive IO_port_right_D0
   set IO_port_right_D0    to "1"
end vector

vector Dat_left_D1_0_W
   initialize to Keep_values_left
   drive IO_port_left_D1
   set IO_port_left_D1     to "0"
end vector

vector Dat_left_D1_1_W
   initialize to Keep_values_left
   drive IO_port_left_D1
   set IO_port_left_D1     to "1"
end vector

vector Dat_right_D1_0_W
   initialize to Keep_values_right
   drive IO_port_right_D1
   set IO_port_right_D1    to "0"
end vector

vector Dat_right_D1_1_W
   initialize to Keep_values_right
   drive IO_port_right_D1
   set IO_port_right_D1    to "1"
end vector

vector Dat_left_D1_0_R
   initialize to Keep_values_left
   receive IO_port_left_D1
   set IO_port_left_D1     to "0"
end vector

vector Dat_left_D1_1_R
   initialize to Keep_values_left
   receive IO_port_left_D1
   set IO_port_left_D1     to "1"
end vector

vector Dat_right_D1_0_R
   initialize to Keep_values_right
   receive IO_port_right_D1
   set IO_port_right_D1    to "0"
end vector

vector Dat_right_D1_1_R
   initialize to Keep_values_right
   receive IO_port_right_D1
   set IO_port_right_D1    to "1"
end vector

vector Dat_left_D2_0_W
   initialize to Keep_values_left
   drive IO_port_left_D2
   set IO_port_left_D2     to "0"
end vector

vector Dat_left_D2_1_W
   initialize to Keep_values_left
   drive IO_port_left_D2
   set IO_port_left_D2     to "1"
end vector

vector Dat_right_D2_0_W
   initialize to Keep_values_right
   drive IO_port_right_D2
   set IO_port_right_D2    to "0"
end vector

vector Dat_right_D2_1_W
   initialize to Keep_values_right
   drive IO_port_right_D2
   set IO_port_right_D2    to "1"
end vector

vector Dat_left_D2_0_R
   initialize to Keep_values_left
   receive IO_port_left_D2
   set IO_port_left_D2     to "0"
end vector

vector Dat_left_D2_1_R
   initialize to Keep_values_left
   receive IO_port_left_D2
   set IO_port_left_D2     to "1"
end vector

vector Dat_right_D2_0_R
   initialize to Keep_values_right
   receive IO_port_right_D2
   set IO_port_right_D2    to "0"
end vector

vector Dat_right_D2_1_R
   initialize to Keep_values_right
   receive IO_port_right_D2
   set IO_port_right_D2    to "1"
end vector

vector Dat_left_D3_0_W
   initialize to Keep_values_left
   drive IO_port_left_D3
   set IO_port_left_D3     to "0"
end vector

vector Dat_left_D3_1_W
   initialize to Keep_values_left
   drive IO_port_left_D3
   set IO_port_left_D3     to "1"
end vector

vector Dat_right_D3_0_W
   initialize to Keep_values_right
   drive IO_port_right_D3
   set IO_port_right_D3    to "0"
end vector

vector Dat_right_D3_1_W
   initialize to Keep_values_right
   drive IO_port_right_D3
   set IO_port_right_D3    to "1"
end vector

vector Dat_left_D3_0_R
   initialize to Keep_values_left
   receive IO_port_left_D3
   set IO_port_left_D3     to "0"
end vector

vector Dat_left_D3_1_R
   initialize to Keep_values_left
   receive IO_port_left_D3
   set IO_port_left_D3     to "1"
end vector

vector Dat_right_D3_0_R
   initialize to Keep_values_right
   receive IO_port_right_D3
   set IO_port_right_D3    to "0"
end vector

vector Dat_right_D3_1_R
   initialize to Keep_values_right
   receive IO_port_right_D3
   set IO_port_right_D3    to "1"
end vector

vector Dat_left_D4_0_W
   initialize to Keep_values_left
   drive IO_port_left_D4
   set IO_port_left_D4     to "0"
end vector

vector Dat_left_D4_1_W
   initialize to Keep_values_left
   drive IO_port_left_D4
   set IO_port_left_D4     to "1"
end vector

vector Dat_right_D4_0_W
   initialize to Keep_values_right
   drive IO_port_right_D4
   set IO_port_right_D4    to "0"
end vector

vector Dat_right_D4_1_W
   initialize to Keep_values_right
   drive IO_port_right_D4
   set IO_port_right_D4    to "1"
end vector

vector Dat_left_D4_0_R
   initialize to Keep_values_left
   receive IO_port_left_D4
   set IO_port_left_D4     to "0"
end vector

vector Dat_left_D4_1_R
   initialize to Keep_values_left
   receive IO_port_left_D4
   set IO_port_left_D4     to "1"
end vector

vector Dat_right_D4_0_R
   initialize to Keep_values_right
   receive IO_port_right_D4
   set IO_port_right_D4    to "0"
end vector

vector Dat_right_D4_1_R
   initialize to Keep_values_right
   receive IO_port_right_D4
   set IO_port_right_D4    to "1"
end vector

vector Dat_left_D5_0_W
   initialize to Keep_values_left
   drive IO_port_left_D5
   set IO_port_left_D5     to "0"
end vector

vector Dat_left_D5_1_W
   initialize to Keep_values_left
   drive IO_port_left_D5
   set IO_port_left_D5     to "1"
end vector

vector Dat_right_D5_0_W
   initialize to Keep_values_right
   drive IO_port_right_D5
   set IO_port_right_D5    to "0"
end vector

vector Dat_right_D5_1_W
   initialize to Keep_values_right
   drive IO_port_right_D5
   set IO_port_right_D5    to "1"
end vector

vector Dat_left_D5_0_R
   initialize to Keep_values_left
   receive IO_port_left_D5
   set IO_port_left_D5     to "0"
end vector

vector Dat_left_D5_1_R
   initialize to Keep_values_left
   receive IO_port_left_D5
   set IO_port_left_D5     to "1"
end vector

vector Dat_right_D5_0_R
   initialize to Keep_values_right
   receive IO_port_right_D5
   set IO_port_right_D5    to "0"
end vector

vector Dat_right_D5_1_R
   initialize to Keep_values_right
   receive IO_port_right_D5
   set IO_port_right_D5    to "1"
end vector

vector Dat_left_D6_0_W
   initialize to Keep_values_left
   drive IO_port_left_D6
   set IO_port_left_D6     to "0"
end vector

vector Dat_left_D6_1_W
   initialize to Keep_values_left
   drive IO_port_left_D6
   set IO_port_left_D6     to "1"
end vector

vector Dat_right_D6_0_W
   initialize to Keep_values_right
   drive IO_port_right_D6
   set IO_port_right_D6    to "0"
end vector

vector Dat_right_D6_1_W
   initialize to Keep_values_right
   drive IO_port_right_D6
   set IO_port_right_D6    to "1"
end vector

vector Dat_left_D6_0_R
   initialize to Keep_values_left
   receive IO_port_left_D6
   set IO_port_left_D6     to "0"
end vector

vector Dat_left_D6_1_R
   initialize to Keep_values_left
   receive IO_port_left_D6
   set IO_port_left_D6     to "1"
end vector

vector Dat_right_D6_0_R
   initialize to Keep_values_right
   receive IO_port_right_D6
   set IO_port_right_D6    to "0"
end vector

vector Dat_right_D6_1_R
   initialize to Keep_values_right
   receive IO_port_right_D6
   set IO_port_right_D6    to "1"
end vector

vector Dat_left_D7_0_W
   initialize to Keep_values_left
   drive IO_port_left_D7
   set IO_port_left_D7     to "0"
end vector

vector Dat_left_D7_1_W
   initialize to Keep_values_left
   drive IO_port_left_D7
   set IO_port_left_D7     to "1"
end vector

vector Dat_right_D7_0_W
   initialize to Keep_values_right
   drive IO_port_right_D7
   set IO_port_right_D7    to "0"
end vector

vector Dat_right_D7_1_W
   initialize to Keep_values_right
   drive IO_port_right_D7
   set IO_port_right_D7    to "1"
end vector

vector Dat_left_D7_0_R
   initialize to Keep_values_left
   receive IO_port_left_D7
   set IO_port_left_D7     to "0"
end vector

vector Dat_left_D7_1_R
   initialize to Keep_values_left
   receive IO_port_left_D7
   set IO_port_left_D7     to "1"
end vector

vector Dat_right_D7_0_R
   initialize to Keep_values_right
   receive IO_port_right_D7
   set IO_port_right_D7    to "0"
end vector

vector Dat_right_D7_1_R
   initialize to Keep_values_right
   receive IO_port_right_D7
   set IO_port_right_D7    to "1"
end vector

!**********************************************************************
!********************  SUBROUTINE   SECTION     ***********************
!**********************************************************************


sub Write_left(Add,Dat)

   execute Add
   execute RW_bar_left_low
   execute Dat
   execute RW_bar_left_hi

end sub

sub Write_right(Add,Dat)

   execute Add
   execute RW_bar_right_low
   execute Dat
   execute RW_bar_right_hi

end sub

sub Write_left_keep_both(Add,Dat)

   execute Add
   execute RW_bar_left_low_B
   execute Dat
   execute RW_bar_left_hi_B

end sub

sub Write_right_keep_both(Add,Dat)

   execute Add
   execute RW_bar_right_low_B
   execute Dat
   execute RW_bar_right_hi_B

end sub

sub Read_keep_both(Add,Dat)

   execute Add
   execute Dat

end sub

sub Read(Add,Dat)             !Either side

   execute Add
   execute Dat

end sub

!**********************************************************************
!*************************  UNIT   SECTION    *************************
!**********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest Left D0 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_D0_0_W)
   call Read(Add_left_0000000000,Dat_left_D0_0_R)

   call Write_left(Add_left_0000000000,Dat_left_D0_1_W)
   call Read(Add_left_0000000000,Dat_left_D0_1_R)

end unit

unit   "awaretest Left D1 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_D1_0_W)
   call Read(Add_left_0000000000,Dat_left_D1_0_R)

   call Write_left(Add_left_0000000000,Dat_left_D1_1_W)
   call Read(Add_left_0000000000,Dat_left_D1_1_R)

end unit

unit   "awaretest Left D2 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_D2_0_W)
   call Read(Add_left_0000000000,Dat_left_D2_0_R)

   call Write_left(Add_left_0000000000,Dat_left_D2_1_W)
   call Read(Add_left_0000000000,Dat_left_D2_1_R)

end unit

unit   "awaretest Left D3 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_D3_0_W)
   call Read(Add_left_0000000000,Dat_left_D3_0_R)

   call Write_left(Add_left_0000000000,Dat_left_D3_1_W)
   call Read(Add_left_0000000000,Dat_left_D3_1_R)

end unit

unit   "awaretest Left D4 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_D4_0_W)
   call Read(Add_left_0000000000,Dat_left_D4_0_R)

   call Write_left(Add_left_0000000000,Dat_left_D4_1_W)
   call Read(Add_left_0000000000,Dat_left_D4_1_R)

end unit

unit   "awaretest Left D5 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_D5_0_W)
   call Read(Add_left_0000000000,Dat_left_D5_0_R)

   call Write_left(Add_left_0000000000,Dat_left_D5_1_W)
   call Read(Add_left_0000000000,Dat_left_D5_1_R)

end unit

unit   "awaretest Left D6 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_D6_0_W)
   call Read(Add_left_0000000000,Dat_left_D6_0_R)

   call Write_left(Add_left_0000000000,Dat_left_D6_1_W)
   call Read(Add_left_0000000000,Dat_left_D6_1_R)

end unit

unit   "awaretest Left D7 Test"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_D7_0_W)
   call Read(Add_left_0000000000,Dat_left_D7_0_R)

   call Write_left(Add_left_0000000000,Dat_left_D7_1_W)
   call Read(Add_left_0000000000,Dat_left_D7_1_R)

end unit

unit   "awaretest Right D0 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Dat_Right_D0_0_W)
   call Read(Add_Right_0000000000,Dat_Right_D0_0_R)

   call Write_Right(Add_Right_0000000000,Dat_Right_D0_1_W)
   call Read(Add_Right_0000000000,Dat_Right_D0_1_R)

end unit

unit   "awaretest Right D1 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Dat_Right_D1_0_W)
   call Read(Add_Right_0000000000,Dat_Right_D1_0_R)

   call Write_Right(Add_Right_0000000000,Dat_Right_D1_1_W)
   call Read(Add_Right_0000000000,Dat_Right_D1_1_R)

end unit

unit   "awaretest Right D2 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Dat_Right_D2_0_W)
   call Read(Add_Right_0000000000,Dat_Right_D2_0_R)

   call Write_Right(Add_Right_0000000000,Dat_Right_D2_1_W)
   call Read(Add_Right_0000000000,Dat_Right_D2_1_R)

end unit

unit   "awaretest Right D3 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Dat_Right_D3_0_W)
   call Read(Add_Right_0000000000,Dat_Right_D3_0_R)

   call Write_Right(Add_Right_0000000000,Dat_Right_D3_1_W)
   call Read(Add_Right_0000000000,Dat_Right_D3_1_R)

end unit

unit   "awaretest Right D4 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Dat_Right_D4_0_W)
   call Read(Add_Right_0000000000,Dat_Right_D4_0_R)

   call Write_Right(Add_Right_0000000000,Dat_Right_D4_1_W)
   call Read(Add_Right_0000000000,Dat_Right_D4_1_R)

end unit

unit   "awaretest Right D5 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Dat_Right_D5_0_W)
   call Read(Add_Right_0000000000,Dat_Right_D5_0_R)

   call Write_Right(Add_Right_0000000000,Dat_Right_D5_1_W)
   call Read(Add_Right_0000000000,Dat_Right_D5_1_R)

end unit

unit   "awaretest Right D6 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Dat_Right_D6_0_W)
   call Read(Add_Right_0000000000,Dat_Right_D6_0_R)

   call Write_Right(Add_Right_0000000000,Dat_Right_D6_1_W)
   call Read(Add_Right_0000000000,Dat_Right_D6_1_R)

end unit

unit   "awaretest Right D7 Test"

   execute Set_values_Right

   call Write_Right(Add_Right_0000000000,Dat_Right_D7_0_W)
   call Read(Add_Right_0000000000,Dat_Right_D7_0_R)

   call Write_Right(Add_Right_0000000000,Dat_Right_D7_1_W)
   call Read(Add_Right_0000000000,Dat_Right_D7_1_R)

end unit

unit "Read and Write Left Port"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_00_W)
   call Write_left(Add_left_1000000000,Dat_left_01_W)
   call Write_left(Add_left_0100000000,Dat_left_02_W)
   call Write_left(Add_left_0010000000,Dat_left_04_W)
   call Write_left(Add_left_0001000000,Dat_left_08_W)
   call Write_left(Add_left_0000100000,Dat_left_10_W)
   call Write_left(Add_left_0000010000,Dat_left_20_W)
   call Write_left(Add_left_0000001000,Dat_left_40_W)
   call Write_left(Add_left_0000000100,Dat_left_80_W)
   call Write_left(Add_left_0000000010,Dat_left_81_W)
   call Write_left(Add_left_0000000001,Dat_left_82_W)

   call Read(Add_left_0000000000,Dat_left_00_R)
   call Read(Add_left_1000000000,Dat_left_01_R)
   call Read(Add_left_0100000000,Dat_left_02_R)
   call Read(Add_left_0010000000,Dat_left_04_R)
   call Read(Add_left_0001000000,Dat_left_08_R)
   call Read(Add_left_0000100000,Dat_left_10_R)
   call Read(Add_left_0000010000,Dat_left_20_R)
   call Read(Add_left_0000001000,Dat_left_40_R)
   call Read(Add_left_0000000100,Dat_left_80_R)
   call Read(Add_left_0000000010,Dat_left_81_R)
   call Read(Add_left_0000000001,Dat_left_82_R)

end unit

unit "Read and Write Right Port"

   execute Set_values_right

   call Write_right(Add_right_0000000000,Dat_right_00_W)
   call Write_right(Add_right_1000000000,Dat_right_01_W)
   call Write_right(Add_right_0100000000,Dat_right_02_W)
   call Write_right(Add_right_0010000000,Dat_right_04_W)
   call Write_right(Add_right_0001000000,Dat_right_08_W)
   call Write_right(Add_right_0000100000,Dat_right_10_W)
   call Write_right(Add_right_0000010000,Dat_right_20_W)
   call Write_right(Add_right_0000001000,Dat_right_40_W)
   call Write_right(Add_right_0000000100,Dat_right_80_W)
   call Write_right(Add_right_0000000010,Dat_right_81_W)
   call Write_right(Add_right_0000000001,Dat_right_82_W)

   call Read(Add_right_0000000000,Dat_right_00_R)
   call Read(Add_right_1000000000,Dat_right_01_R)
   call Read(Add_right_0100000000,Dat_right_02_R)
   call Read(Add_right_0010000000,Dat_right_04_R)
   call Read(Add_right_0001000000,Dat_right_08_R)
   call Read(Add_right_0000100000,Dat_right_10_R)
   call Read(Add_right_0000010000,Dat_right_20_R)
   call Read(Add_right_0000001000,Dat_right_40_R)
   call Read(Add_right_0000000100,Dat_right_80_R)
   call Read(Add_right_0000000010,Dat_right_81_R)
   call Read(Add_right_0000000001,Dat_right_82_R)

end unit

unit "Test With Left Port in Read-Only Mode"

   execute Set_values_right

   call Write_right(Add_right_0000000000,Dat_right_00_W)
   call Write_right(Add_right_1000000000,Dat_right_01_W)
   call Write_right(Add_right_0100000000,Dat_right_02_W)
   call Write_right(Add_right_0010000000,Dat_right_04_W)
   call Write_right(Add_right_0001000000,Dat_right_08_W)
   call Write_right(Add_right_0000100000,Dat_right_10_W)
   call Write_right(Add_right_0000010000,Dat_right_20_W)
   call Write_right(Add_right_0000001000,Dat_right_40_W)
   call Write_right(Add_right_0000000100,Dat_right_80_W)
   call Write_right(Add_right_0000000010,Dat_right_81_W)
   call Write_right(Add_right_0000000001,Dat_right_82_W)

   execute Set_values_left

   call Read(Add_left_0000000000,Dat_left_00_R)
   call Read(Add_left_1000000000,Dat_left_01_R)
   call Read(Add_left_0100000000,Dat_left_02_R)
   call Read(Add_left_0010000000,Dat_left_04_R)
   call Read(Add_left_0001000000,Dat_left_08_R)
   call Read(Add_left_0000100000,Dat_left_10_R)
   call Read(Add_left_0000010000,Dat_left_20_R)
   call Read(Add_left_0000001000,Dat_left_40_R)
   call Read(Add_left_0000000100,Dat_left_80_R)
   call Read(Add_left_0000000010,Dat_left_81_R)
   call Read(Add_left_0000000001,Dat_left_82_R)

end unit

unit "Test With Right Port in Read-Only Mode"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_00_W)
   call Write_left(Add_left_1000000000,Dat_left_01_W)
   call Write_left(Add_left_0100000000,Dat_left_02_W)
   call Write_left(Add_left_0010000000,Dat_left_04_W)
   call Write_left(Add_left_0001000000,Dat_left_08_W)
   call Write_left(Add_left_0000100000,Dat_left_10_W)
   call Write_left(Add_left_0000010000,Dat_left_20_W)
   call Write_left(Add_left_0000001000,Dat_left_40_W)
   call Write_left(Add_left_0000000100,Dat_left_80_W)
   call Write_left(Add_left_0000000010,Dat_left_81_W)
   call Write_left(Add_left_0000000001,Dat_left_82_W)

   execute Set_values_right

   call Read(Add_right_0000000000,Dat_right_00_R)
   call Read(Add_right_1000000000,Dat_right_01_R)
   call Read(Add_right_0100000000,Dat_right_02_R)
   call Read(Add_right_0010000000,Dat_right_04_R)
   call Read(Add_right_0001000000,Dat_right_08_R)
   call Read(Add_right_0000100000,Dat_right_10_R)
   call Read(Add_right_0000010000,Dat_right_20_R)
   call Read(Add_right_0000001000,Dat_right_40_R)
   call Read(Add_right_0000000100,Dat_right_80_R)
   call Read(Add_right_0000000010,Dat_right_81_R)
   call Read(Add_right_0000000001,Dat_right_82_R)

end unit

unit "Test CE_bar_left With Write and Read"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_00_W)
   call Read(Add_left_0000000000,Dat_left_00_R)

   execute CE_bar_left_hi

   call Write_left(Add_left_0000000000,Dat_left_FF_W)

   execute CE_bar_left_low

   call Read(Add_left_0000000000,Dat_left_00_R)

end unit

unit "Test CE_bar_left With Left Port in Read-Only Mode"

   execute Set_values_right

   call Write_right(Add_right_0000000000,Dat_right_00_W)

   execute Set_values_left

   call Read(Add_left_0000000000,Dat_left_00_R)

   execute CE_bar_left_hi

   call Read(Add_left_0000000000,Dat_left_FF_R)

   execute CE_bar_left_low

   call Read(Add_left_0000000000,Dat_left_00_R)

end unit

unit "Test CE_bar_right With Write and Read"

   execute Set_values_right

   call Write_right(Add_right_0000000000,Dat_right_00_W)
   call Read(Add_right_0000000000,Dat_right_00_R)

   execute CE_bar_right_hi

   call Write_right(Add_right_0000000000,Dat_right_FF_W)

   execute CE_bar_right_low

   call Read(Add_right_0000000000,Dat_right_00_R)

end unit

unit "Test CE_bar_right With Right Port in Read-Only Mode"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_00_W)

   execute Set_values_right

   call Read(Add_right_0000000000,Dat_right_00_R)

   execute CE_bar_right_hi

   call Read(Add_right_0000000000,Dat_right_FF_R)

   execute CE_bar_right_low

   call Read(Add_right_0000000000,Dat_right_00_R)

end unit

unit "Test BUSY_bar_left With Write and Read"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_00_W)
   call Read(Add_left_0000000000,Dat_left_00_R)

   execute BUSY_bar_left_low

   call Write_left(Add_left_0000000000,Dat_left_FF_W)

   execute BUSY_bar_left_hi

   call Read(Add_left_0000000000,Dat_left_00_R)

end unit

unit "Test BUSY_bar_right With Write and Read"

   execute Set_values_right

   call Write_right(Add_right_0000000000,Dat_right_00_W)
   call Read(Add_right_0000000000,Dat_right_00_R)

   execute BUSY_bar_right_low

   call Write_right(Add_right_0000000000,Dat_right_FF_W)

   execute BUSY_bar_right_hi

   call Read(Add_right_0000000000,Dat_right_00_R)

end unit

!
!  The next 4 units require Pull-ups on the Data lines
!

unit "Test OE_bar_left With Write and Read"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_00_W)
   call Read(Add_left_0000000000,Dat_left_00_R)

   execute OE_bar_left_hi

   call Read(Add_left_0000000000,Dat_left_FF_R)

   execute OE_bar_left_low

   call Read(Add_left_0000000000,Dat_left_00_R)

end unit

unit "Test OE_bar_left With Left Port in Read-Only Mode"

   execute Set_values_right

   call Write_right(Add_right_0000000000,Dat_right_00_W)

   execute Set_values_left

   call Read(Add_left_0000000000,Dat_left_00_R)

   execute OE_bar_left_hi

   call Read(Add_left_0000000000,Dat_left_FF_R)

   execute OE_bar_left_low

   call Read(Add_left_0000000000,Dat_left_00_R)

end unit

unit "Test OE_bar_right With Write and Read"

   execute Set_values_right

   call Write_right(Add_right_0000000000,Dat_right_00_W)
   call Read(Add_right_0000000000,Dat_right_00_R)

   execute OE_bar_right_hi

   call Read(Add_right_0000000000,Dat_right_FF_R)

   execute OE_bar_right_low

   call Read(Add_right_0000000000,Dat_right_00_R)

end unit

unit "Test OE_bar_right With Right Port in Read-Only Mode"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_00_W)

   execute Set_values_right

   call Read(Add_right_0000000000,Dat_right_00_R)

   execute OE_bar_right_hi

   call Read(Add_right_0000000000,Dat_right_FF_R)

   execute OE_bar_right_low

   call Read(Add_right_0000000000,Dat_right_00_R)

end unit

! The following two units have been added because the device correctly
! performs 'reads' and 'writes' when RW_bar is stuck at "1"
! (beleive it or not.).

unit "Test RW_bar, Left Port"

   execute Set_values_left

   call Write_left(Add_left_0000000000,Dat_left_00_W)
   execute Add_left_0000000000
   execute Dat_left_00_R

   execute RW_bar_left_low
   execute RW_bar_left_low
   execute Dat_left_FF_R

end unit

unit "Test RW_bar, Right Port"

   execute Set_values_right

   call Write_right(Add_right_0000000000,Dat_right_00_W)
   execute Add_right_0000000000
   execute Dat_right_00_R

   execute RW_bar_right_low
   execute RW_bar_right_low
   execute Dat_right_FF_R

end unit

unit "Test INT_bar_left"

   execute Set_values_both

   execute INT_bar_left_hi_Setup
   execute INT_bar_left_hi_Setup
   execute INT_bar_left_hi_Setup
   execute INT_bar_left_hi_Setup
   execute INT_bar_left_hi

   execute Set_values_both

   execute INT_bar_left_low_Setup
   execute INT_bar_left_low_Setup
   execute INT_bar_left_low_Setup
   execute INT_bar_left_low_Setup
   execute INT_bar_left_low

   execute Set_values_both

   execute INT_bar_left_hi_Setup
   execute INT_bar_left_hi_Setup
   execute INT_bar_left_hi_Setup
   execute INT_bar_left_hi_Setup
   execute INT_bar_left_hi

end unit

unit "Test INT_bar_right"

   execute Set_values_both

   execute INT_bar_right_hi_Setup
   execute INT_bar_right_hi_Setup
   execute INT_bar_right_hi_Setup
   execute INT_bar_right_hi_Setup
   execute INT_bar_right_hi

   execute Set_values_both

   execute INT_bar_right_low_Setup
   execute INT_bar_right_low_Setup
   execute INT_bar_right_low_Setup
   execute INT_bar_right_low_Setup
   execute INT_bar_right_low

   execute Set_values_both

   execute INT_bar_right_hi_Setup
   execute INT_bar_right_hi_Setup
   execute INT_bar_right_hi_Setup
   execute INT_bar_right_hi_Setup
   execute INT_bar_right_hi

end unit

unit "Test for Accidentally Tied Busy_bar and INT_bar, Left"

   execute Set_values_both

call Write_left_keep_Both(Add_left_0000000000_B,Dat_left_00_W_B)
call Write_left_keep_Both(Add_left_0000000001_B,Dat_left_01_W_B)
call Read_keep_Both(Add_left_0000000000_B,Dat_left_00_R_B)


   execute INT_bar_left_low_Setup
   execute INT_bar_left_low_Setup
   execute INT_bar_left_low_Setup
   execute INT_bar_left_low
   execute Dat_left_00_R_B
call Read_keep_Both(Add_left_0000000001_B,Dat_left_01_R_B)

end unit

unit "Test for Accidentally Tied Busy_bar and INT_bar, Right"

   execute Set_values_both

call Write_right_keep_Both(Add_right_0000000000_B,Dat_right_00_W_B)
call Write_right_keep_Both(Add_right_0000000001_B,Dat_right_01_W_B)
call Read_keep_Both(Add_right_0000000000_B,Dat_right_00_R_B)


   execute INT_bar_right_low_Setup
   execute INT_bar_right_low_Setup
   execute INT_bar_right_low_Setup
   execute INT_bar_right_low
   execute Dat_right_00_R_B
call Read_keep_Both(Add_right_0000000001_B,Dat_right_01_R_B)

end unit

!!! End of Test