!!!!    6    0    1  986571412  Vd23c                                         

! Device           : 9130
! Function         : Static RAM 3-state 1k x 4
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

assign    VCC            to pins   22
assign    GND            to pins   11

assign    Address        to pins   4,3,2,1,16,17,18,19,20,21

assign    Data           to pins   8,7,6,5
assign    Data_D0        to pins   5    !AT Added for minimum pin test.
assign    Data_D1        to pins   6    !AT Added for minimum pin test.
assign    Data_D2        to pins   7    !AT Added for minimum pin test.
assign    Data_D3        to pins   8    !AT Added for minimum pin test.

assign    Write_enable_bar      to pins   15
assign    Chip_select_bar       to pins   14
assign    Chip_enable           to pins   12
assign    Output_enable         to pins   13
assign    Output_disable        to pins   9
assign    Memory_status         to pins   10

family    TTL

power     VCC, GND

inputs    Address, Write_enable_bar, Chip_select_bar
inputs    Chip_enable, Output_enable, Output_disable

outputs   Memory_status

bidirectional  Data
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.

disable   Data   with Output_enable         to   "0"
disable   Data   with Output_disable        to   "1"

when Output_enable is "0" inactive Data
when Output_disable is "1" inactive Data
when  Write_enable_bar  is "1"   outputs  Data
when  Write_enable_bar  is "0"   inputs   Data

trace Data to Address, Write_enable_bar, Chip_select_bar
trace Data to Chip_enable, Output_enable, Output_disable

trace Memory_status to Address, Write_enable_bar, Chip_select_bar
trace Memory_status to Chip_enable, Output_enable, Output_disable
!***************************************************************
!***************************************************************

vector   Read_disable
     set  Address            to  "kkkkkkkkkk"
     set  Chip_enable        to  "0"
     set  Chip_select_bar    to  "1"
     set  Output_enable      to  "1"
     set  Output_disable     to  "1"
     set  Write_enable_bar   to  "1"
end vector

vector   Write_disable
          drive  Data
     set  Data               to  "kkkk"
     set  Chip_enable        to  "0"
     set  Chip_select_bar    to  "1"
     set  Output_enable      to  "0"
     set  Output_disable     to  "1"
     set  Write_enable_bar   to  "1"
end vector

vector   Chip_select
     set  Chip_enable        to  "0"
     set  Chip_select_bar    to  "0"
     set  Output_enable      to  "0"
     set  Output_disable     to  "0"
     set  Write_enable_bar   to  "1"
end vector

vector   Chip_select_false
     set  Chip_enable        to  "0"
     set  Chip_select_bar    to  "1"
     set  Output_enable      to  "0"
     set  Output_disable     to  "0"
     set  Write_enable_bar   to  "1"
end vector

vector   Memory_status_0
     set  Chip_enable        to  "k"
     set  Chip_select_bar    to  "k"
     set  Output_enable      to  "k"
     set  Output_disable     to  "k"
     set  Write_enable_bar   to  "k"
     set  Memory_status      to  "0"
end vector

vector   Memory_status_1
          drive  Data
     set  Data               to  "kkkk"
     set  Chip_enable        to  "k"
     set  Chip_select_bar    to  "k"
     set  Output_enable      to  "k"
     set  Output_disable     to  "k"
     set  Write_enable_bar   to  "k"
     set  Memory_status      to  "1"
end vector

vector   Chip_enabled
     set  Address            to  "kkkkkkkkkk"
     set  Chip_enable        to  "1"
     set  Chip_select_bar    to  "k"
     set  Output_enable      to  "k"
     set  Output_disable     to  "k"
     set  Write_enable_bar   to  "k"
end vector

vector   Chip_enable_false
     set  Address            to  "kkkkkkkkkk"
     set  Chip_enable        to  "0"
     set  Chip_select_bar    to  "k"
     set  Output_enable      to  "k"
     set  Output_disable     to  "k"
     set  Write_enable_bar   to  "k"
end vector

vector   Write_enable
          drive  Data
     set  Data               to  "kkkk"
     set  Address            to  "kkkkkkkkkk"
     set  Chip_enable        to  "k"
     set  Chip_select_bar    to  "k"
     set  Output_enable      to  "k"
     set  Output_disable     to  "k"
     set  Write_enable_bar   to  "k"
end vector

vector   Data_Valid_In
     set  Chip_enable        to  "k"
     set  Chip_select_bar    to  "1"
     set  Output_enable      to  "k"
     set  Output_disable     to  "k"
     set  Write_enable_bar   to  "0"
end vector

vector   Data_Valid_Out
     set  Chip_enable        to  "1"
     set  Chip_select_bar    to  "1"
     set  Output_enable      to  "1"
     set  Output_disable     to  "0"
     set  Write_enable_bar   to  "k"
end vector

vector   Address_0000000000
     initialize to Chip_select
     set  Address     to "0000000000"
end vector

vector   Address_0000000001
     initialize to Chip_select
     set  Address     to "0000000001"
end vector

vector   Address_0000000011
     initialize to Chip_select
     set  Address     to "0000000011"
end vector

vector   Address_0000000111
     initialize to Chip_select
     set  Address     to "0000000111"
end vector

vector   Address_0000001111
     initialize to Chip_select
     set  Address     to "0000001111"
end vector

vector   Address_0000011111
     initialize to Chip_select
     set  Address     to "0000011111"
end vector

vector   Address_0000111111
     initialize to Chip_select
     set  Address     to "0000111111"
end vector

vector   Address_0001111111
     initialize to Chip_select
     set  Address     to "0001111111"
end vector

vector   Address_0011111111
     initialize to Chip_select
     set  Address     to "0011111111"
end vector

vector   Address_0111111111
     initialize to Chip_select
     set  Address     to "0111111111"
end vector

vector   Address_1111111111
     initialize to Chip_select
     set  Address     to "1111111111"
end vector

vector   Data_In_0000
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "0000"
end vector

vector   Data_In_0001
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "0001"
end vector

vector   Data_In_0011
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "0011"
end vector

vector   Data_In_0111
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "0111"
end vector

vector   Data_In_1111
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "1111"
end vector

vector   Data_In_1110
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "1110"
end vector

vector   Data_In_1100
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "1100"
end vector

vector   Data_In_1000
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "1000"
end vector

vector   Data_In_1010
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "1010"
end vector

vector   Data_In_0101
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "0101"
end vector

vector   Data_In_0010
     initialize to Data_Valid_In
          drive  Data
     set  Data            to "0010"
end vector

vector   Read_Data_0000
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "0000"
end vector

vector   Read_Data_0001
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "0001"
end vector

vector   Read_Data_0011
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "0011"
end vector

vector   Read_Data_0111
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "0111"
end vector

vector   Read_Data_1111
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "1111"
end vector

vector   Read_Data_1110
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "1110"
end vector

vector   Read_Data_1100
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "1100"
end vector

vector   Read_Data_1000
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "1000"
end vector

vector   Read_Data_1010
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "1010"
end vector

vector   Read_Data_0101
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "0101"
end vector

vector   Read_Data_0010
     initialize to Data_Valid_Out
          receive  Data
     set  Data            to "0010"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   Write_d_D0
          drive  Data_D0
     set  Data_D0            to  "k"
     set  Chip_enable        to  "0"
     set  Chip_select_bar    to  "1"
     set  Output_enable      to  "0"
     set  Output_disable     to  "1"
     set  Write_enable_bar   to  "1"
end vector

vector   Write_d_D1
          drive  Data_D1
     set  Data_D1            to  "k"
     set  Chip_enable        to  "0"
     set  Chip_select_bar    to  "1"
     set  Output_enable      to  "0"
     set  Output_disable     to  "1"
     set  Write_enable_bar   to  "1"
end vector

vector   Write_d_D2
          drive  Data_D2
     set  Data_D2            to  "k"
     set  Chip_enable        to  "0"
     set  Chip_select_bar    to  "1"
     set  Output_enable      to  "0"
     set  Output_disable     to  "1"
     set  Write_enable_bar   to  "1"
end vector

vector   Write_d_D3
          drive  Data_D3
     set  Data_D3            to  "k"
     set  Chip_enable        to  "0"
     set  Chip_select_bar    to  "1"
     set  Output_enable      to  "0"
     set  Output_disable     to  "1"
     set  Write_enable_bar   to  "1"
end vector

vector   Write_en_D0
          drive  Data_D0
     set  Data_D0            to  "k"
     set  Address            to  "kkkkkkkkkk"
     set  Chip_enable        to  "k"
     set  Chip_select_bar    to  "k"
     set  Output_enable      to  "k"
     set  Output_disable     to  "k"
     set  Write_enable_bar   to  "k"
end vector

vector   Write_en_D1
          drive  Data_D1
     set  Data_D1            to  "k"
     set  Address            to  "kkkkkkkkkk"
     set  Chip_enable        to  "k"
     set  Chip_select_bar    to  "k"
     set  Output_enable      to  "k"
     set  Output_disable     to  "k"
     set  Write_enable_bar   to  "k"
end vector

vector   Write_en_D2
          drive  Data_D2
     set  Data_D2            to  "k"
     set  Address            to  "kkkkkkkkkk"
     set  Chip_enable        to  "k"
     set  Chip_select_bar    to  "k"
     set  Output_enable      to  "k"
     set  Output_disable     to  "k"
     set  Write_enable_bar   to  "k"
end vector

vector   Write_en_D3
          drive  Data_D3
     set  Data_D3            to  "k"
     set  Address            to  "kkkkkkkkkk"
     set  Chip_enable        to  "k"
     set  Chip_select_bar    to  "k"
     set  Output_enable      to  "k"
     set  Output_disable     to  "k"
     set  Write_enable_bar   to  "k"
end vector

vector   Data_In_D0_0
     initialize to Data_Valid_In
          drive  Data_D0
     set  Data_D0         to "0"
end vector

vector   Data_In_D0_1
     initialize to Data_Valid_In
          drive  Data_D0
     set  Data_D0         to "1"
end vector

vector   Data_In_D1_0
     initialize to Data_Valid_In
          drive  Data_D1
     set  Data_D1         to "0"
end vector

vector   Data_In_D1_1
     initialize to Data_Valid_In
          drive  Data_D1
     set  Data_D1         to "1"
end vector

vector   Data_In_D2_0
     initialize to Data_Valid_In
          drive  Data_D2
     set  Data_D2         to "0"
end vector

vector   Data_In_D2_1
     initialize to Data_Valid_In
          drive  Data_D2
     set  Data_D2         to "1"
end vector

vector   Data_In_D3_0
     initialize to Data_Valid_In
          drive  Data_D3
     set  Data_D3         to "0"
end vector

vector   Data_In_D3_1
     initialize to Data_Valid_In
          drive  Data_D3
     set  Data_D3         to "1"
end vector

vector   Read_Data_D0_0
     initialize to Data_Valid_Out
          receive  Data_D0
     set  Data_D0         to "0"
end vector

vector   Read_Data_D0_1
     initialize to Data_Valid_Out
          receive  Data_D0
     set  Data_D0         to "1"
end vector

vector   Read_Data_D1_0
     initialize to Data_Valid_Out
          receive  Data_D1
     set  Data_D1         to "0"
end vector

vector   Read_Data_D1_1
     initialize to Data_Valid_Out
          receive  Data_D1
     set  Data_D1         to "1"
end vector

vector   Read_Data_D2_0
     initialize to Data_Valid_Out
          receive  Data_D2
     set  Data_D2         to "0"
end vector

vector   Read_Data_D2_1
     initialize to Data_Valid_Out
          receive  Data_D2
     set  Data_D2         to "1"
end vector

vector   Read_Data_D3_0
     initialize to Data_Valid_Out
          receive  Data_D3
     set  Data_D3         to "0"
end vector

vector   Read_Data_D3_1
     initialize to Data_Valid_Out
          receive  Data_D3
     set  Data_D3         to "1"
end vector

!*****************************************************************************
!*****************************************************************************

sub  Write_Data (Address,Data)
      execute     Address
      execute     Chip_enabled
      execute     Data
      execute     Write_enable
      execute     Write_disable
end sub

sub  Read_Data (Address,Data)
      execute     Address
      execute     Chip_enabled
      execute     Data
      execute     Read_disable
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_In_Dx, Write_en_Dx, Write_d_Dx)
      execute     Address
      execute     Chip_enabled
      execute     Data_In_Dx
      execute     Write_en_Dx
      execute     Write_d_Dx
end sub

!*****************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

  call Write_data_Dx (Address_0000000000, Data_In_D0_0, Write_en_D0, Write_d_D0)
  call Read_data (Address_0000000000, Read_data_D0_0)

  call Write_data_Dx (Address_0000000000, Data_In_D0_1, Write_en_D0, Write_d_D0)
  call Read_data (Address_0000000000, Read_data_D0_1)

end unit

unit   "awaretest D1 Test"

  call Write_data_Dx (Address_0000000000, Data_In_D1_0, Write_en_D1, Write_d_D1)
  call Read_data (Address_0000000000, Read_data_D1_0)

  call Write_data_Dx (Address_0000000000, Data_In_D1_1, Write_en_D1, Write_d_D1)
  call Read_data (Address_0000000000, Read_data_D1_1)

end unit

unit   "awaretest D2 Test"

  call Write_data_Dx (Address_0000000000, Data_In_D2_0, Write_en_D2, Write_d_D2)
  call Read_data (Address_0000000000, Read_data_D2_0)

  call Write_data_Dx (Address_0000000000, Data_In_D2_1, Write_en_D2, Write_d_D2)
  call Read_data (Address_0000000000, Read_data_D2_1)

end unit

unit   "awaretest D3 Test"

  call Write_data_Dx (Address_0000000000, Data_In_D3_0, Write_en_D3, Write_d_D3)
  call Read_data (Address_0000000000, Read_data_D3_0)

  call Write_data_Dx (Address_0000000000, Data_In_D3_1, Write_en_D3, Write_d_D3)
  call Read_data (Address_0000000000, Read_data_D3_1)

end unit

unit "RAM test"
     call Write_data (Address_0000000000, Data_In_0000)
     call Write_data (Address_0000000001, Data_In_0001)
     call Write_data (Address_0000000011, Data_In_0011)
     call Write_data (Address_0000000111, Data_In_0111)
     call Write_data (Address_0000001111, Data_In_1111)
     call Write_data (Address_0000011111, Data_In_1110)
     call Write_data (Address_0000111111, Data_In_1100)
     call Write_data (Address_0001111111, Data_In_1000)
     call Write_data (Address_0011111111, Data_In_1010)
     call Write_data (Address_0111111111, Data_In_0101)
     call Write_data (Address_1111111111, Data_In_0010)
     call Read_data (Address_0000000000, Read_data_0000)
     call Read_data (Address_0000000001, Read_data_0001)
     call Read_data (Address_0000000011, Read_data_0011)
     call Read_data (Address_0000000111, Read_data_0111)
     call Read_data (Address_0000001111, Read_data_1111)
     call Read_data (Address_0000011111, Read_data_1110)
     call Read_data (Address_0000111111, Read_data_1100)
     call Read_data (Address_0001111111, Read_data_1000)
     call Read_data (Address_0011111111, Read_data_1010)
     call Read_data (Address_0111111111, Read_data_0101)
     call Read_data (Address_1111111111, Read_data_0010)
end unit

unit "Chip_select_false"
     call Write_data (Address_0000000000, Data_In_1111)
     execute Address_0000000000
     execute Chip_select_false
     execute Chip_enabled
     execute Data_In_0000
     execute Write_enable
     execute Write_disable
     call Read_data (Address_0000000000, Read_data_1111)
end unit

unit "Chip_enable_false"
     call Write_data (Address_0000000000, Data_In_1111)
     execute Address_0000000000
     execute Chip_enable_false
     execute Data_In_0000
     execute Write_enable
     execute Write_disable
     call Read_data (Address_0000000000, Read_data_1111)
end unit

unit "Memory_status"
     execute Address_0000000000
     execute Chip_enabled
     execute Data_In_1111
     execute Memory_status_1
     execute Write_enable
     execute Write_disable
     execute Memory_status_0
     call Read_data (Address_0000000000, Read_data_1111)
end unit

!    End of test