!!!! 6 0 1 986331172 V206b ! Device : 9122 ! Function : RAM 256 x 4 ! revision : B.01.00 ! safeguard : high_out_mos ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." sequential !warning "Pull-ups are required to test high-impedance outputs." vector cycle 500n receive delay 400n assign VCC to pins 22 assign GND to pins 8 assign Address to pins 7,6,5,21,1,2,3,4 assign Data_in to pins 15,13,11,9 assign D3 to pins 15 assign D2 to pins 13 assign D1 to pins 11 assign D0 to pins 9 assign Data_out to pins 16,14,12,10 assign Q3 to pins 16 assign Q2 to pins 14 assign Q1 to pins 12 assign Q0 to pins 10 assign Chip_select_bar_1 to pins 19 assign Chip_select_2 to pins 17 assign Output_Enable_bar to pins 18 assign Write_Enable_bar to pins 20 family TTL power VCC, GND inputs Address,Data_in,Chip_select_bar_1,Chip_select_2 inputs Output_Enable_bar,Write_Enable_bar inputs D0, D1, D2, D3 !AT Added for minimum pin test. outputs Data_out outputs Q0, Q1, Q2, Q3 !AT Added for minimum pin test. disable Data_out with Chip_select_bar_1 to "1" disable Data_out with Chip_select_2 to "0" disable Data_out with Output_Enable_bar to "1" when Chip_select_bar_1 is "1" inactive Data_out when Chip_select_2 is "0" inactive Data_out when Output_Enable_bar is "1" inactive Data_out trace Q3 to D3 trace Q2 to D2 trace Q1 to D1 trace Q0 to D0 trace Data_out to Address, Chip_select_bar_1, Chip_select_2 trace Data_out to Output_Enable_bar, Write_Enable_bar set load on groups Data_out to pull up !************************************************************************* !************************************************************************* vector Setup set Chip_Select_bar_1 to "1" set Chip_Select_2 to "0" set Write_Enable_bar to "1" set Output_Enable_bar to "0" set Address to "00000000" set Data_in to "0000" end vector vector Keep_On_Control set Address to "kkkkkkkk" set Data_In to "kkkk" set Output_Enable_bar to "k" set Chip_Select_bar_1 to "k" set Chip_Select_2 to "k" set Write_Enable_bar to "k" end vector vector Output_Disable initialize to Keep_On_Control set Output_Enable_bar to "1" end vector vector Write initialize to Keep_On_Control set Write_Enable_bar to "0" end vector vector Read initialize to Keep_On_Control set Write_Enable_bar to "1" end vector vector Chip_Select initialize to Keep_On_Control set Chip_Select_bar_1 to "0" set Chip_Select_2 to "1" end vector vector CS1bar_Disable initialize to Keep_On_Control set Chip_Select_bar_1 to "1" set Chip_Select_2 to "1" end vector vector CS2_Disable initialize to Keep_On_Control set Chip_Select_bar_1 to "0" set Chip_Select_2 to "0" end vector vector Data_In_5 initialize to Keep_On_Control set Data_In to "0101" end vector vector Data_In_A initialize to Keep_On_Control set Data_In to "1010" end vector vector Data_Out_5 initialize to Keep_On_Control set Data_Out to "0101" end vector vector Data_Out_A initialize to Keep_On_Control set Write_Enable_bar to "1" set Data_Out to "1010" end vector vector Address_in_counter initialize to Keep_On_Control set Write_Enable_bar to "1" set Address to "00000000" upcounter Address end vector vector Address_out_counter initialize to Keep_On_Control set Data_out to "0101" set Address to "00000000" upcounter Address end vector vector Data_Out_9 initialize to Keep_On_Control set Write_Enable_bar to "1" set Data_Out to "1001" end vector vector Data_Out_0 initialize to Keep_On_Control set Write_Enable_bar to "1" set Data_Out to "0000" end vector vector Data_Out_F initialize to Keep_On_Control set Write_Enable_bar to "1" set Data_Out to "1111" end vector vector Data_In_9 initialize to Keep_On_Control set Data_In to "1001" end vector vector Address_7 initialize to Keep_On_Control set Address to "00000111" end vector !AT The following vectors have been added for a minimum pins test. Any !AT vectors that references the data bus was copied and modified to reference !AT only a single pin of the data bus. vector Setup_Dx set Chip_Select_bar_1 to "1" set Chip_Select_2 to "0" set Write_Enable_bar to "1" set Output_Enable_bar to "1" set Address to "00000000" end vector vector Keep_On_Control_Dx set Chip_Select_bar_1 to "k" set Chip_Select_2 to "k" set Write_Enable_bar to "k" set Output_Enable_bar to "k" set Address to "kkkkkkkk" end vector vector Chip_Select_Dx set Chip_Select_bar_1 to "0" set Chip_Select_2 to "1" set Write_Enable_bar to "k" set Output_Enable_bar to "k" set Address to "kkkkkkkk" end vector vector Data_In_D0_0 initialize to Keep_On_Control_Dx set D0 to "0" end vector vector Data_In_D0_1 initialize to Keep_On_Control_Dx set D0 to "1" end vector vector Data_In_D1_0 initialize to Keep_On_Control_Dx set D1 to "0" end vector vector Data_In_D1_1 initialize to Keep_On_Control_Dx set D1 to "1" end vector vector Data_In_D2_0 initialize to Keep_On_Control_Dx set D2 to "0" end vector vector Data_In_D2_1 initialize to Keep_On_Control_Dx set D2 to "1" end vector vector Data_In_D3_0 initialize to Keep_On_Control_Dx set D3 to "0" end vector vector Data_In_D3_1 initialize to Keep_On_Control_Dx set D3 to "1" end vector vector Write_D0 set Chip_Select_bar_1 to "k" set Chip_Select_2 to "k" set Write_Enable_bar to "0" set Output_Enable_bar to "k" set Address to "kkkkkkkk" set D0 to "k" end vector vector Write_D1 set Chip_Select_bar_1 to "k" set Chip_Select_2 to "k" set Write_Enable_bar to "0" set Output_Enable_bar to "k" set Address to "kkkkkkkk" set D1 to "k" end vector vector Write_D2 set Chip_Select_bar_1 to "k" set Chip_Select_2 to "k" set Write_Enable_bar to "0" set Output_Enable_bar to "k" set Address to "kkkkkkkk" set D2 to "k" end vector vector Write_D3 set Chip_Select_bar_1 to "k" set Chip_Select_2 to "k" set Write_Enable_bar to "0" set Output_Enable_bar to "k" set Address to "kkkkkkkk" set D3 to "k" end vector vector Read_D0 set Chip_Select_bar_1 to "k" set Chip_Select_2 to "k" set Write_Enable_bar to "1" set Output_Enable_bar to "0" set Address to "kkkkkkkk" set D0 to "k" end vector vector Read_D1 set Chip_Select_bar_1 to "k" set Chip_Select_2 to "k" set Write_Enable_bar to "1" set Output_Enable_bar to "0" set Address to "kkkkkkkk" set D1 to "k" end vector vector Read_D2 set Chip_Select_bar_1 to "k" set Chip_Select_2 to "k" set Write_Enable_bar to "1" set Output_Enable_bar to "0" set Address to "kkkkkkkk" set D2 to "k" end vector vector Read_D3 set Chip_Select_bar_1 to "k" set Chip_Select_2 to "k" set Write_Enable_bar to "1" set Output_Enable_bar to "0" set Address to "kkkkkkkk" set D3 to "k" end vector vector Data_Out_Q0_0 initialize to Keep_On_Control_Dx set D0 to "k" set Q0 to "0" end vector vector Data_Out_Q0_1 initialize to Keep_On_Control_Dx set D0 to "k" set Q0 to "1" end vector vector Data_Out_Q1_0 initialize to Keep_On_Control_Dx set D1 to "k" set Q1 to "0" end vector vector Data_Out_Q1_1 initialize to Keep_On_Control_Dx set D1 to "k" set Q1 to "1" end vector vector Data_Out_Q2_0 initialize to Keep_On_Control_Dx set D2 to "k" set Q2 to "0" end vector vector Data_Out_Q2_1 initialize to Keep_On_Control_Dx set D2 to "k" set Q2 to "1" end vector vector Data_Out_Q3_0 initialize to Keep_On_Control_Dx set D3 to "k" set Q3 to "0" end vector vector Data_Out_Q3_1 initialize to Keep_On_Control_Dx set D3 to "k" set Q3 to "1" end vector !******************************************************************************* !******************************************************************************* !AT The following AwareTest units have been added for minimum pins tests. Each !AT unit tests a separate data pin starting with D0. unit "awaretest D0 Test" execute Setup_Dx execute Chip_Select_Dx execute Data_In_D0_0 execute Write_D0 execute Read_D0 execute Data_Out_Q0_0 execute Setup_Dx execute Chip_Select_Dx execute Data_In_D0_1 execute Write_D0 execute Read_D0 execute Data_Out_Q0_1 end unit unit "awaretest D1 Test" execute Setup_Dx execute Chip_Select_Dx execute Data_In_D1_0 execute Write_D1 execute Read_D1 execute Data_Out_Q1_0 execute Setup_Dx execute Chip_Select_Dx execute Data_In_D1_1 execute Write_D1 execute Read_D1 execute Data_Out_Q1_1 end unit unit "awaretest D2 Test" execute Setup_Dx execute Chip_Select_Dx execute Data_In_D2_0 execute Write_D2 execute Read_D2 execute Data_Out_Q2_0 execute Setup_Dx execute Chip_Select_Dx execute Data_In_D2_1 execute Write_D2 execute Read_D2 execute Data_Out_Q2_1 end unit unit "awaretest D3 Test" execute Setup_Dx execute Chip_Select_Dx execute Data_In_D3_0 execute Write_D3 execute Read_D3 execute Data_Out_Q3_0 execute Setup_Dx execute Chip_Select_Dx execute Data_In_D3_1 execute Write_D3 execute Read_D3 execute Data_Out_Q3_1 end unit unit "Test" execute Setup preset counter Address_In_Counter execute Chip_Select execute Data_In_5 repeat 256 times count Address_In_counter execute Write end repeat execute Chip_select execute Read preset counter Address_Out_Counter execute Data_Out_5 execute Data_In_A repeat 256 times count Address_Out_counter execute Write execute Data_Out_A end repeat end unit unit "Test_Cs_1" execute Setup execute Address_7 execute Chip_Select execute Data_In_9 execute Write execute Read execute Data_Out_9 execute CS1bar_Disable execute Data_In_5 execute Write execute Read execute Chip_Select execute Data_Out_9 end unit unit "Test_Cs_2" execute Setup execute Address_7 execute Chip_Select execute Data_In_9 execute Write execute Read execute Data_Out_9 execute CS2_Disable execute Data_In_5 execute Write execute Read execute Chip_Select execute Data_Out_9 end unit unit "Output_Enable_bar" execute Setup execute Address_7 execute Chip_Select execute Data_In_9 execute Write execute Read execute Data_Out_9 execute Output_Disable execute Data_Out_F end unit ! End of Test