!!!!    6    0    1  986772545  V2959                                         

! Device           : 8128
! Function         : Static RAM 3-state 2k x 8
! revision         : B.01.00
! safeguard        : low_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle  1.0u
receive delay 900n

!warning "Pull-ups are required to test high-impedance outputs."

assign    VCC            to pins   24
assign    GND            to pins   12

assign    Address        to pins   19,22,23,1,2,3,4,5
assign    Address        to pins   6,7,8

assign    Data           to pins   17,16,15,14,13,11,10,9
assign    Data_D0        to pins   9    !AT Added for minimum pin test.
assign    Data_D1        to pins   10   !AT Added for minimum pin test.
assign    Data_D2        to pins   11   !AT Added for minimum pin test.
assign    Data_D3        to pins   13   !AT Added for minimum pin test.
assign    Data_D4        to pins   14   !AT Added for minimum pin test.
assign    Data_D5        to pins   15   !AT Added for minimum pin test.
assign    Data_D6        to pins   16   !AT Added for minimum pin test.
assign    Data_D7        to pins   17   !AT Added for minimum pin test.

assign    CEbar          to pins   18
assign    WEbar          to pins   21
assign    OEbar          to pins   20

family    TTL

power          VCC, GND

inputs         Address, CEbar,WEbar,OEbar

bidirectional  Data
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.
bidirectional  Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test.

set load on groups Data      to pull up

disable   Data      with CEbar      to "1"
disable   Data      with OEbar      to "1"

when OEbar is "1" inactive Data
when CEbar is "1" inactive Data
when WEbar is "1" outputs Data
when WEbar is "0" inputs Data

trace Data to Address, CEbar,WEbar,OEbar
!***************************************************************
!***************************************************************

vector   Setup
   drive Data
   set   Data           to "00000000"
   set   CEbar          to "0"
   set   OEbar          to "0"
   set   WEbar          to "1"
end vector

vector   Hold_ctrl
   set   CEbar          to "k"
   set   OEbar          to "k"
   set   WEbar          to "k"
end   vector

vector   CEbar_false
   set   CEbar          to "1"
   set   OEbar          to "0"
   set   WEbar          to "1"
end   vector

vector   OEbar_false
   set   CEbar          to "0"
   set   OEbar          to "1"
   set   WEbar          to "1"
end   vector

vector    Hold_ctrl_Read
   set  Address       to   "kkkkkkkkkkk"
   set  CEbar         to   "k"
   set  WEbar         to   "k"
   set  OEbar         to   "k"
end vector

vector    Hold_ctrl_Write
   set  Address       to   "kkkkkkkkkkk"
   set  CEbar         to   "k"
   set  WEbar         to   "k"
   set  OEbar         to   "k"
end vector

vector   Read_enable
   set   Address     to    "kkkkkkkkkkk"
   set   CEbar       to    "k"
   set   WEbar       to    "1"
   set   OEbar       to    "k"
end   vector

vector   Write_enable
   set   Address     to    "kkkkkkkkkkk"
   set   CEbar       to    "k"
   set   WEbar       to    "0"
   set   OEbar       to    "k"
end   vector

vector    Address_00000000000
   initialize     to   Hold_ctrl
   set  Address   to   "00000000000"
end vector

vector    Address_00000000001
   initialize     to   Hold_ctrl
   set  Address   to   "00000000001"
end vector

vector    Address_00000000011
   initialize     to   Hold_ctrl
   set  Address   to   "00000000011"
end vector

vector    Address_00000000111
   initialize     to   Hold_ctrl
   set  Address   to   "00000000111"
end vector

vector    Address_00000001111
   initialize     to   Hold_ctrl
   set  Address   to   "00000001111"
end vector

vector    Address_00000011111
   initialize     to   Hold_ctrl
   set  Address   to   "00000011111"
end vector

vector    Address_00000111111
   initialize     to   Hold_ctrl
   set  Address   to   "00000111111"
end vector

vector    Address_00001111111
   initialize     to   Hold_ctrl
   set  Address   to   "00001111111"
end vector

vector    Address_00011111111
   initialize     to   Hold_ctrl
   set  Address   to   "00011111111"
end vector

vector    Address_00111111111
   initialize     to   Hold_ctrl
   set  Address   to   "00111111111"
end vector

vector    Address_01111111111
   initialize     to   Hold_ctrl
   set  Address   to   "01111111111"
end vector

vector    Address_11111111111
   initialize     to   Hold_ctrl
   set  Address   to   "11111111111"
end vector

vector    Data_write_00000000
   initialize to   Hold_ctrl_Write
   drive    Data
   set Data to   "00000000"
end vector

vector    Data_write_00000001
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "00000001"
end vector

vector    Data_write_00000011
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "00000011"
end vector

vector    Data_write_00000111
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "00000111"
end vector

vector    Data_write_00001111
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "00001111"
end vector

vector    Data_write_00011111
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "00011111"
end vector

vector    Data_write_00111111
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "00111111"
end vector

vector    Data_write_01111111
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "01111111"
end vector

vector    Data_write_11111111
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "11111111"
end vector

vector    Data_write_10101010
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "10101010"
end vector

vector    Data_write_01010101
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "01010101"
end vector

vector    Data_write_11110000
   initialize to  Hold_ctrl_Write
   drive    Data
   set Data to   "11110000"
end vector

vector    Data_read_00000000
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "00000000"
end vector

vector    Data_read_00000001
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "00000001"
end vector

vector    Data_read_00000011
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "00000011"
end vector

vector    Data_read_00000111
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "00000111"
end vector

vector    Data_read_00001111
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "00001111"
end vector

vector    Data_read_00011111
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "00011111"
end vector

vector    Data_read_00111111
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "00111111"
end vector

vector    Data_read_01111111
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "01111111"
end vector

vector    Data_read_11111111
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "11111111"
end vector

vector    Data_read_10101010
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "10101010"
end vector

vector    Data_read_01010101
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "01010101"
end vector

vector    Data_read_11110000
   initialize to  Hold_ctrl_Read
   receive Data
   set Data to   "11110000"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   Setup_D0
   drive Data_D0
   set   Data_D0        to "0"
   set   CEbar          to "0"
   set   OEbar          to "0"
   set   WEbar          to "1"
end vector

vector   Setup_D1
   drive Data_D1
   set   Data_D1        to "0"
   set   CEbar          to "0"
   set   OEbar          to "0"
   set   WEbar          to "1"
end vector

vector   Setup_D2
   drive Data_D2
   set   Data_D2        to "0"
   set   CEbar          to "0"
   set   OEbar          to "0"
   set   WEbar          to "1"
end vector

vector   Setup_D3
   drive Data_D3
   set   Data_D3        to "0"
   set   CEbar          to "0"
   set   OEbar          to "0"
   set   WEbar          to "1"
end vector

vector   Setup_D4
   drive Data_D4
   set   Data_D4        to "0"
   set   CEbar          to "0"
   set   OEbar          to "0"
   set   WEbar          to "1"
end vector

vector   Setup_D5
   drive Data_D5
   set   Data_D5        to "0"
   set   CEbar          to "0"
   set   OEbar          to "0"
   set   WEbar          to "1"
end vector

vector   Setup_D6
   drive Data_D6
   set   Data_D6        to "0"
   set   CEbar          to "0"
   set   OEbar          to "0"
   set   WEbar          to "1"
end vector

vector   Setup_D7
   drive Data_D7
   set   Data_D7        to "0"
   set   CEbar          to "0"
   set   OEbar          to "0"
   set   WEbar          to "1"
end vector

vector    Data_write_D0_0
   initialize to   Hold_ctrl_Write
   drive    Data_D0
   set Data_D0    to   "0"
end vector

vector    Data_write_D0_1
   initialize to   Hold_ctrl_Write
   drive    Data_D0
   set Data_D0    to   "1"
end vector

vector    Data_write_D1_0
   initialize to   Hold_ctrl_Write
   drive    Data_D1
   set Data_D1    to   "0"
end vector

vector    Data_write_D1_1
   initialize to   Hold_ctrl_Write
   drive    Data_D1
   set Data_D1    to   "1"
end vector

vector    Data_write_D2_0
   initialize to   Hold_ctrl_Write
   drive    Data_D2
   set Data_D2    to   "0"
end vector

vector    Data_write_D2_1
   initialize to   Hold_ctrl_Write
   drive    Data_D2
   set Data_D2    to   "1"
end vector

vector    Data_write_D3_0
   initialize to   Hold_ctrl_Write
   drive    Data_D3
   set Data_D3    to   "0"
end vector

vector    Data_write_D3_1
   initialize to   Hold_ctrl_Write
   drive    Data_D3
   set Data_D3    to   "1"
end vector

vector    Data_write_D4_0
   initialize to   Hold_ctrl_Write
   drive    Data_D4
   set Data_D4    to   "0"
end vector

vector    Data_write_D4_1
   initialize to   Hold_ctrl_Write
   drive    Data_D4
   set Data_D4    to   "1"
end vector

vector    Data_write_D5_0
   initialize to   Hold_ctrl_Write
   drive    Data_D5
   set Data_D5    to   "0"
end vector

vector    Data_write_D5_1
   initialize to   Hold_ctrl_Write
   drive    Data_D5
   set Data_D5    to   "1"
end vector

vector    Data_write_D6_0
   initialize to   Hold_ctrl_Write
   drive    Data_D6
   set Data_D6    to   "0"
end vector

vector    Data_write_D6_1
   initialize to   Hold_ctrl_Write
   drive    Data_D6
   set Data_D6    to   "1"
end vector

vector    Data_write_D7_0
   initialize to   Hold_ctrl_Write
   drive    Data_D7
   set Data_D7    to   "0"
end vector

vector    Data_write_D7_1
   initialize to   Hold_ctrl_Write
   drive    Data_D7
   set Data_D7    to   "1"
end vector

vector    Data_read_D0_0
   initialize to  Hold_ctrl_Read
   receive Data_D0
   set Data_D0    to   "0"
end vector

vector    Data_read_D0_1
   initialize to  Hold_ctrl_Read
   receive Data_D0
   set Data_D0    to   "1"
end vector

vector    Data_read_D1_0
   initialize to  Hold_ctrl_Read
   receive Data_D1
   set Data_D1    to   "0"
end vector

vector    Data_read_D1_1
   initialize to  Hold_ctrl_Read
   receive Data_D1
   set Data_D1    to   "1"
end vector

vector    Data_read_D2_0
   initialize to  Hold_ctrl_Read
   receive Data_D2
   set Data_D2    to   "0"
end vector

vector    Data_read_D2_1
   initialize to  Hold_ctrl_Read
   receive Data_D2
   set Data_D2    to   "1"
end vector

vector    Data_read_D3_0
   initialize to  Hold_ctrl_Read
   receive Data_D3
   set Data_D3    to   "0"
end vector

vector    Data_read_D3_1
   initialize to  Hold_ctrl_Read
   receive Data_D3
   set Data_D3    to   "1"
end vector

vector    Data_read_D4_0
   initialize to  Hold_ctrl_Read
   receive Data_D4
   set Data_D4    to   "0"
end vector

vector    Data_read_D4_1
   initialize to  Hold_ctrl_Read
   receive Data_D4
   set Data_D4    to   "1"
end vector

vector    Data_read_D5_0
   initialize to  Hold_ctrl_Read
   receive Data_D5
   set Data_D5    to   "0"
end vector

vector    Data_read_D5_1
   initialize to  Hold_ctrl_Read
   receive Data_D5
   set Data_D5    to   "1"
end vector

vector    Data_read_D6_0
   initialize to  Hold_ctrl_Read
   receive Data_D6
   set Data_D6    to   "0"
end vector

vector    Data_read_D6_1
   initialize to  Hold_ctrl_Read
   receive Data_D6
   set Data_D6    to   "1"
end vector

vector    Data_read_D7_0
   initialize to  Hold_ctrl_Read
   receive Data_D7
   set Data_D7    to   "0"
end vector

vector    Data_read_D7_1
   initialize to  Hold_ctrl_Read
   receive Data_D7
   set Data_D7    to   "1"
end vector

!***************************************************************
!***************************************************************

sub  Write_data (Address, Data)
   execute   Address
   execute   Write_enable
   execute   Data
end sub

sub  Read_data (Address, Data)
   execute   Address
   execute   Read_enable
   execute   Data
end sub

!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

   execute  Setup_D0
   call Write_data (Address_00000000000, Data_write_D0_0)
   execute  Setup_D0
   call Read_data (Address_00000000000, Data_read_D0_0)

   execute  Setup_D0
   call Write_data (Address_00000000000, Data_write_D0_1)
   execute  Setup_D0
   call Read_data (Address_00000000000, Data_read_D0_1)

end unit

unit   "awaretest D1 Test"

   execute  Setup_D1
   call Write_data (Address_00000000000, Data_write_D1_0)
   execute  Setup_D1
   call Read_data (Address_00000000000, Data_read_D1_0)

   execute  Setup_D1
   call Write_data (Address_00000000000, Data_write_D1_1)
   execute  Setup_D1
   call Read_data (Address_00000000000, Data_read_D1_1)

end unit

unit   "awaretest D2 Test"

   execute  Setup_D2
   call Write_data (Address_00000000000, Data_write_D2_0)
   execute  Setup_D2
   call Read_data (Address_00000000000, Data_read_D2_0)

   execute  Setup_D2
   call Write_data (Address_00000000000, Data_write_D2_1)
   execute  Setup_D2
   call Read_data (Address_00000000000, Data_read_D2_1)

end unit

unit   "awaretest D3 Test"

   execute  Setup_D3
   call Write_data (Address_00000000000, Data_write_D3_0)
   execute  Setup_D3
   call Read_data (Address_00000000000, Data_read_D3_0)

   execute  Setup_D3
   call Write_data (Address_00000000000, Data_write_D3_1)
   execute  Setup_D3
   call Read_data (Address_00000000000, Data_read_D3_1)

end unit

unit   "awaretest D4 Test"

   execute  Setup_D4
   call Write_data (Address_00000000000, Data_write_D4_0)
   execute  Setup_D4
   call Read_data (Address_00000000000, Data_read_D4_0)

   execute  Setup_D4
   call Write_data (Address_00000000000, Data_write_D4_1)
   execute  Setup_D4
   call Read_data (Address_00000000000, Data_read_D4_1)

end unit

unit   "awaretest D5 Test"

   execute  Setup_D5
   call Write_data (Address_00000000000, Data_write_D5_0)
   execute  Setup_D5
   call Read_data (Address_00000000000, Data_read_D5_0)

   execute  Setup_D5
   call Write_data (Address_00000000000, Data_write_D5_1)
   execute  Setup_D5
   call Read_data (Address_00000000000, Data_read_D5_1)

end unit

unit   "awaretest D6 Test"

   execute  Setup_D6
   call Write_data (Address_00000000000, Data_write_D6_0)
   execute  Setup_D6
   call Read_data (Address_00000000000, Data_read_D6_0)

   execute  Setup_D6
   call Write_data (Address_00000000000, Data_write_D6_1)
   execute  Setup_D6
   call Read_data (Address_00000000000, Data_read_D6_1)

end unit

unit   "awaretest D7 Test"

   execute  Setup_D7
   call Write_data (Address_00000000000, Data_write_D7_0)
   execute  Setup_D7
   call Read_data (Address_00000000000, Data_read_D7_0)

   execute  Setup_D7
   call Write_data (Address_00000000000, Data_write_D7_1)
   execute  Setup_D7
   call Read_data (Address_00000000000, Data_read_D7_1)

end unit

unit "RAM test"
   execute  Setup
   call Write_data (Address_00000000000, Data_write_00000000)
   call Write_data (Address_00000000001, Data_write_00000001)
   call Write_data (Address_00000000011, Data_write_00000011)
   call Write_data (Address_00000000111, Data_write_00000111)
   call Write_data (Address_00000001111, Data_write_00001111)
   call Write_data (Address_00000011111, Data_write_00011111)
   call Write_data (Address_00000111111, Data_write_00111111)
   call Write_data (Address_00001111111, Data_write_01111111)
   call Write_data (Address_00011111111, Data_write_11111111)
   call Write_data (Address_00111111111, Data_write_01010101)
   call Write_data (Address_01111111111, Data_write_10101010)
   call Write_data (Address_11111111111, Data_write_11110000)

   execute  Setup

   call Read_data (Address_00000000000, Data_read_00000000)
   call Read_data (Address_00000000001, Data_read_00000001)
   call Read_data (Address_00000000011, Data_read_00000011)
   call Read_data (Address_00000000111, Data_read_00000111)
   call Read_data (Address_00000001111, Data_read_00001111)
   call Read_data (Address_00000011111, Data_read_00011111)
   call Read_data (Address_00000111111, Data_read_00111111)
   call Read_data (Address_00001111111, Data_read_01111111)
   call Read_data (Address_00011111111, Data_read_11111111)
   call Read_data (Address_00111111111, Data_read_01010101)
   call Read_data (Address_01111111111, Data_read_10101010)
   call Read_data (Address_11111111111, Data_read_11110000)
end unit

unit "test chip enable"
   execute  Setup
   call     Write_data (Address_00000001111,Data_write_01010101)
   execute  CEbar_false
   execute  Address_00000001111
   execute  Read_enable

!     If pull_ups added, uncomment this line
!  execute  Data_read_11111111

!     Else, if pull-downs, uncomment this line
!  execute  Data_read_00000000
end   unit

unit "test outputs enable"
   execute  Setup
   call     Write_data (Address_00000001111,Data_write_01010101)
   execute  OEbar_false
   execute  Address_00000001111
   execute  Read_enable
   execute  Data_read_11111111
end   unit




!    End of test