!!!!    6    0    1  986495789  Vb724                                         

! Device           : 74ls219
! Function         : 16 x 4-bit static RAM
! revision         : B.01.00
! safeguard        : high_out_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

assign    VCC            to pins   16
assign    GND            to pins   8

assign    Address        to pins   13,14,15,1

assign    Data_In        to pins   12,10,6,4
assign    Data_Out       to pins   11,9,7,5

assign  Data_in_D0  to pins 4    !AT Added for minimum pin test.
assign  Data_in_D1  to pins 6    !AT Added for minimum pin test.
assign  Data_in_D2  to pins 10   !AT Added for minimum pin test.
assign  Data_in_D3  to pins 12   !AT Added for minimum pin test.

assign  Data_out_D0 to pins 5    !AT Added for minimum pin test.
assign  Data_out_D1 to pins 7    !AT Added for minimum pin test.
assign  Data_out_D2 to pins 9    !AT Added for minimum pin test.
assign  Data_out_D3 to pins 11   !AT Added for minimum pin test.

assign    Chip_select_bar       to pins   2
assign    Write_enable_bar      to pins   3

family    TTL

power     VCC, GND

inputs    Address, Write_enable_bar, Chip_select_bar ,Data_In
inputs Data_in_D0, Data_in_D1, Data_in_D2, Data_in_D3      !AT Added for min pin test.

outputs    Data_Out
outputs Data_out_D0, Data_out_D1, Data_out_D2, Data_out_D3 !AT Added for min pin test.

when  Chip_select_bar is "1" inactive  Data_out

trace   Data_out to Address, Write_enable_bar, Chip_select_bar ,Data_In

disable   Data_out   with  Write_enable_bar    to   "1"
disable   Data_out   with  Chip_select_bar     to   "1"

!***************************************************************
!***************************************************************

vector    Disable
     set  Write_enable_bar    to   "1"
     set  Chip_select_bar     to   "1"
end vector

vector    Chip_enable_true
     set  Address             to   "kkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_select_bar     to   "0"
end vector

vector    Write_enable
     set  Address             to   "kkkk"
     set  Write_enable_bar    to   "0"
     set  Chip_select_bar     to   "k"
end vector

vector    Write_enable_true
     set  Address             to   "kkkk"
     set  Write_enable_bar    to   "0"
     set  Chip_select_bar     to   "k"
end vector

vector    Write_enable_false
     set  Data_In             to   "kkkk"
     set  Write_enable_bar    to   "1"
     set  Chip_select_bar     to   "k"
end vector

vector    Chip_enable_false
     set  Data_In             to   "kkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_select_bar     to   "1"
end vector

vector    Read_enable
     set  Address             to   "kkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_select_bar     to   "0"
end vector

vector    Read_disable
     set  Write_enable_bar    to   "k"
     set  Chip_select_bar     to   "1"
end vector

vector    Addr_0000
     initialize to  Disable
     set  Address   to   "0000"
end vector

vector    Addr_0001
     initialize to  Disable
     set  Address   to   "0001"
end vector

vector    Addr_0011
     initialize to  Disable
     set  Address   to   "0011"
end vector

vector    Addr_0111
     initialize to  Disable
     set  Address   to   "0111"
end vector

vector    Addr_1111
     initialize to  Disable
     set  Address   to   "1111"
end vector

vector    Data_write_1111_CE_false
     set Address           to  "kkkk"
     set Write_enable_bar  to  "0"
     set Chip_select_bar   to  "k"
     set Data_In           to  "1111"
end vector

vector    Data_in_0000
     initialize to  Write_enable
     set Data_In       to   "0000"
end vector

vector    Data_in_0001
     initialize to  Write_enable
     set Data_In       to   "0001"
end vector

vector    Data_in_0011
     initialize to  Write_enable
     set Data_In       to   "0011"
end vector

vector    Data_in_0111
     initialize to  Write_enable
     set Data_In       to   "0111"
end vector

vector    Data_in_1111
     initialize to  Write_enable
     set Data_In       to   "1111"
end vector

vector    Data_out_0000
     initialize to  Read_enable
     set Data_out       to   "0000"
end vector

vector    Data_out_0001
     initialize to  Read_enable
     set Data_out       to   "0001"
end vector

vector    Data_out_0011
     initialize to  Read_enable
     set Data_out       to   "0011"
end vector

vector    Data_out_0111
     initialize to  Read_enable
     set Data_out       to   "0111"
end vector

vector    Data_out_1111
     initialize to  Read_enable
     set Data_out       to   "1111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    WEb_hi_D0
     set  Data_In_D0          to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_select_bar     to   "k"
end vector

vector    WEb_hi_D1
     set  Data_In_D1          to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_select_bar     to   "k"
end vector

vector    WEb_hi_D2
     set  Data_In_D2          to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_select_bar     to   "k"
end vector

vector    WEb_hi_D3
     set  Data_In_D3          to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_select_bar     to   "k"
end vector

vector    CE_hi_D0
     set  Data_In_D0          to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_select_bar     to   "1"
end vector

vector    CE_hi_D1
     set  Data_In_D1          to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_select_bar     to   "1"
end vector

vector    CE_hi_D2
     set  Data_In_D2          to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_select_bar     to   "1"
end vector

vector    CE_hi_D3
     set  Data_In_D3          to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_select_bar     to   "1"
end vector

vector    Data_in_D0_0
     initialize to  Write_enable
     set Data_In_D0           to   "0"
end vector

vector    Data_in_D0_1
     initialize to  Write_enable
     set Data_In_D0           to   "1"
end vector

vector    Data_in_D1_0
     initialize to  Write_enable
     set Data_In_D1           to   "0"
end vector

vector    Data_in_D1_1
     initialize to  Write_enable
     set Data_In_D1           to   "1"
end vector

vector    Data_in_D2_0
     initialize to  Write_enable
     set Data_In_D2           to   "0"
end vector

vector    Data_in_D2_1
     initialize to  Write_enable
     set Data_In_D2           to   "1"
end vector

vector    Data_in_D3_0
     initialize to  Write_enable
     set Data_In_D3           to   "0"
end vector

vector    Data_in_D3_1
     initialize to  Write_enable
     set Data_In_D3           to   "1"
end vector

vector    Data_out_D0_0
     initialize to  Read_enable
     set Data_out_D0          to   "0"
end vector

vector    Data_out_D0_1
     initialize to  Read_enable
     set Data_out_D0          to   "1"
end vector

vector    Data_out_D1_0
     initialize to  Read_enable
     set Data_out_D1          to   "0"
end vector

vector    Data_out_D1_1
     initialize to  Read_enable
     set Data_out_D1          to   "1"
end vector

vector    Data_out_D2_0
     initialize to  Read_enable
     set Data_out_D2          to   "0"
end vector

vector    Data_out_D2_1
     initialize to  Read_enable
     set Data_out_D2          to   "1"
end vector

vector    Data_out_D3_0
     initialize to  Read_enable
     set Data_out_D3          to   "0"
end vector

vector    Data_out_D3_1
     initialize to  Read_enable
     set Data_out_D3          to   "1"
end vector

!***************************************************************
!***************************************************************

sub  Write_data (Address, Data)
     execute   Address
     execute   Chip_enable_true
     execute   Data
     execute   Chip_enable_false
     execute   Write_enable_false
end sub

sub  Read_data (Address, Data)
     execute   Address
     execute   Data
     execute   Read_disable
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, CE_hi_Dx, WEb_hi_Dx)
     execute   Address
     execute   Chip_enable_true
     execute   Data_Dx
     execute   CE_hi_Dx
     execute   WEb_hi_Dx
end sub

!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

    call Write_data_Dx (Addr_0000, Data_In_D0_0, CE_hi_D0, WEb_hi_D0)
    call Read_data (Addr_0000, Data_Out_D0_0)

    call Write_data_Dx (Addr_0000, Data_In_D0_1, CE_hi_D0, WEb_hi_D0)
    call Read_data (Addr_0000, Data_Out_D0_1)

end unit

unit   "awaretest D1 Test"

    call Write_data_Dx (Addr_0000, Data_In_D1_0, CE_hi_D1, WEb_hi_D1)
    call Read_data (Addr_0000, Data_Out_D1_0)

    call Write_data_Dx (Addr_0000, Data_In_D1_1, CE_hi_D1, WEb_hi_D1)
    call Read_data (Addr_0000, Data_Out_D1_1)

end unit

unit   "awaretest D2 Test"

    call Write_data_Dx (Addr_0000, Data_In_D2_0, CE_hi_D2, WEb_hi_D2)
    call Read_data (Addr_0000, Data_Out_D2_0)

    call Write_data_Dx (Addr_0000, Data_In_D2_1, CE_hi_D2, WEb_hi_D2)
    call Read_data (Addr_0000, Data_Out_D2_1)

end unit

unit   "awaretest D3 Test"

    call Write_data_Dx (Addr_0000, Data_In_D3_0, CE_hi_D3, WEb_hi_D3)
    call Read_data (Addr_0000, Data_Out_D3_0)

    call Write_data_Dx (Addr_0000, Data_In_D3_1, CE_hi_D3, WEb_hi_D3)
    call Read_data (Addr_0000, Data_Out_D3_1)

end unit

unit "Test RAM  Latch_bar_high"
     call Write_data (Addr_0000, Data_In_1111)
     call Write_data (Addr_0001, Data_In_0111)
     call Write_data (Addr_0011, Data_In_0011)
     call Write_data (Addr_0111, Data_In_0001)
     call Write_data (Addr_1111, Data_In_0000)
     call Read_data (Addr_0000, Data_Out_1111)
     call Read_data (Addr_0001, Data_Out_0111)
     call Read_data (Addr_0011, Data_Out_0011)
     call Read_data (Addr_0111, Data_Out_0001)
     call Read_data (Addr_1111, Data_Out_0000)
end unit

unit "Test  Chip_enable"
     call Write_data (Addr_0000, Data_In_0000)
     execute   Addr_0000
     execute   Chip_enable_false
     execute   Data_write_1111_CE_false
     execute   Write_enable_false
     call Read_data (Addr_0000, Data_Out_0000)
end unit

!    End of test