!!!!    6    0    1  986756931  V9009                                         

! Device           : 74c910
! Function         : Static RAM 3-state 64 x 4
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 1000n
receive delay 900n

assign    VCC            to pins   18
assign    GND            to pins   9

assign    Address        to pins   7,8,10,11,5,6

assign    Data_in        to pins   15,16,2,3
assign    Data_out       to pins   14,17,1,4

assign    Data_in_D0  to pins 3    !AT Added for minimum pin test.
assign    Data_in_D1  to pins 2    !AT Added for minimum pin test.
assign    Data_in_D2  to pins 16   !AT Added for minimum pin test.
assign    Data_in_D3  to pins 15   !AT Added for minimum pin test.

assign    Data_out_D0 to pins 4    !AT Added for minimum pin test.
assign    Data_out_D1 to pins 1    !AT Added for minimum pin test.
assign    Data_out_D2 to pins 17   !AT Added for minimum pin test.
assign    Data_out_D3 to pins 14   !AT Added for minimum pin test.

assign    Write_enable_bar      to pins   13
assign    Memory_enable_bar     to pins   12
assign    Output_disable        to pins   13,12

family    TTL

power     VCC, GND

inputs    Address, Data_in, Write_enable_bar, Memory_enable_bar
inputs Data_in_D0, Data_in_D1, Data_in_D2, Data_in_D3      !AT Added for min pin test.

outputs   Data_out
outputs Data_out_D0, Data_out_D1, Data_out_D2, Data_out_D3 !AT Added for min pin test.

when     Memory_enable_bar    is    "1"   inactive Data_out
when     Write_enable_bar     is    "0"   inactive Data_out

trace    Data_out to  Address,Data_in,Write_enable_bar,Memory_enable_bar

disable   Data_out  with  Output_disable    to   "00"
disable   Data_out  with  Output_disable    to   "01"
disable   Data_out  with  Output_disable    to   "11"

!***************************************************************
!***************************************************************

vector   Disable
     set  Write_enable_bar    to   "1"
     set  Memory_enable_bar   to   "1"
end vector

vector   Address_hold
     set  Address             to   "kkkkkk"
     set  Write_enable_bar    to   "k"
     set  Memory_enable_bar   to   "0"
end vector

vector   Write_enable_true
     set  Address             to   "kkkkkk"
     set  Data_in             to   "kkkk"
     set  Write_enable_bar    to   "0"
     set  Memory_enable_bar   to   "k"
end vector

vector   Write_enable_false
     set  Address             to   "kkkkkk"
     set  Data_in             to   "kkkk"
     set  Write_enable_bar    to   "1"
     set  Memory_enable_bar   to   "k"
end vector

vector   Address_000000
     initialize to  Disable
     set  Address   to   "000000"
end vector

vector   Address_000001
     initialize to  Disable
     set  Address   to   "000001"
end vector

vector   Address_000011
     initialize to  Disable
     set  Address   to   "000011"
end vector

vector   Address_000111
     initialize to  Disable
     set  Address   to   "000111"
end vector

vector   Address_001111
     initialize to  Disable
     set  Address   to   "001111"
end vector

vector   Address_011111
     initialize to  Disable
     set  Address   to   "011111"
end vector

vector   Address_111111
     initialize to  Disable
     set  Address   to   "111111"
end vector

vector  Data_write_0000
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in            to  "0000"
end vector

vector  Data_write_0001
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in            to  "0001"
end vector

vector  Data_write_0011
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in            to  "0011"
end vector

vector  Data_write_0111
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in            to  "0111"
end vector

vector  Data_write_1111
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in            to  "1111"
end vector

vector  Data_write_1010
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in            to  "1010"
end vector

vector  Data_write_0101
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in            to  "0101"
end vector

vector  Data_read_0000
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out           to  "0000"
end vector

vector  Data_read_0001
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out           to  "0001"
end vector

vector  Data_read_0011
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out           to  "0011"
end vector

vector  Data_read_0111
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out           to  "0111"
end vector

vector  Data_read_1111
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out           to  "1111"
end vector

vector  Data_read_1010
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out           to  "1010"
end vector

vector  Data_read_0101
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out           to  "0101"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   WEb_lo_D0
     set  Address             to   "kkkkkk"
     set  Data_in_D0          to   "k"
     set  Write_enable_bar    to   "0"
     set  Memory_enable_bar   to   "k"
end vector

vector   WEb_lo_D1
     set  Address             to   "kkkkkk"
     set  Data_in_D1          to   "k"
     set  Write_enable_bar    to   "0"
     set  Memory_enable_bar   to   "k"
end vector

vector   WEb_lo_D2
     set  Address             to   "kkkkkk"
     set  Data_in_D2          to   "k"
     set  Write_enable_bar    to   "0"
     set  Memory_enable_bar   to   "k"
end vector

vector   WEb_lo_D3
     set  Address             to   "kkkkkk"
     set  Data_in_D3          to   "k"
     set  Write_enable_bar    to   "0"
     set  Memory_enable_bar   to   "k"
end vector

vector   WEb_hi_D0
     set  Address             to   "kkkkkk"
     set  Data_in_D0          to   "k"
     set  Write_enable_bar    to   "1"
     set  Memory_enable_bar   to   "k"
end vector

vector   WEb_hi_D1
     set  Address             to   "kkkkkk"
     set  Data_in_D1          to   "k"
     set  Write_enable_bar    to   "1"
     set  Memory_enable_bar   to   "k"
end vector

vector   WEb_hi_D2
     set  Address             to   "kkkkkk"
     set  Data_in_D2          to   "k"
     set  Write_enable_bar    to   "1"
     set  Memory_enable_bar   to   "k"
end vector

vector   WEb_hi_D3
     set  Address             to   "kkkkkk"
     set  Data_in_D3          to   "k"
     set  Write_enable_bar    to   "1"
     set  Memory_enable_bar   to   "k"
end vector

vector  Data_write_D0_0
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in_D0         to  "0"
end vector

vector  Data_write_D0_1
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in_D0         to  "1"
end vector

vector  Data_write_D1_0
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in_D1         to  "0"
end vector

vector  Data_write_D1_1
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in_D1         to  "1"
end vector

vector  Data_write_D2_0
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in_D2         to  "0"
end vector

vector  Data_write_D2_1
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in_D2         to  "1"
end vector

vector  Data_write_D3_0
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in_D3         to  "0"
end vector

vector  Data_write_D3_1
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_in_D3         to  "1"
end vector

vector  Data_read_D0_0
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out_D0        to  "0"
end vector

vector  Data_read_D0_1
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out_D0        to  "1"
end vector

vector  Data_read_D1_0
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out_D1        to  "0"
end vector

vector  Data_read_D1_1
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out_D1        to  "1"
end vector

vector  Data_read_D2_0
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out_D2        to  "0"
end vector

vector  Data_read_D2_1
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out_D2        to  "1"
end vector

vector  Data_read_D3_0
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out_D3        to  "0"
end vector

vector  Data_read_D3_1
     set Address            to  "kkkkkk"
     set Write_enable_bar   to  "k"
     set Memory_enable_bar  to  "k"
     set Data_out_D3        to  "1"
end vector


!***************************************************************
!***************************************************************

sub  Write_data (Address, Data)
     execute   Address
     execute   Address_hold
     execute   Data
     execute   Write_enable_true
     execute   Write_enable_false
end sub

sub  Read_data (Address, Data)
     execute   Address
     execute   Address_hold
     execute   Data
     execute   Disable
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, WEb_lo_Dx, WEb_hi_Dx)
     execute   Address
     execute   Address_hold
     execute   Data_Dx
     execute   WEb_lo_Dx
     execute   WEb_hi_Dx
end sub

!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

     call Write_data_Dx (Address_000000, Data_write_D0_0, WEb_lo_D0, WEb_hi_D0)
     call Read_data (Address_000000, Data_read_D0_0)

     call Write_data_Dx (Address_000000, Data_write_D0_1, WEb_lo_D0, WEb_hi_D0)
     call Read_data (Address_000000, Data_read_D0_1)

end unit

unit   "awaretest D1 Test"

     call Write_data_Dx (Address_000000, Data_write_D1_0, WEb_lo_D1, WEb_hi_D1)
     call Read_data (Address_000000, Data_read_D1_0)

     call Write_data_Dx (Address_000000, Data_write_D1_1, WEb_lo_D1, WEb_hi_D1)
     call Read_data (Address_000000, Data_read_D1_1)

end unit

unit   "awaretest D2 Test"

     call Write_data_Dx (Address_000000, Data_write_D2_0, WEb_lo_D2, WEb_hi_D2)
     call Read_data (Address_000000, Data_read_D2_0)

     call Write_data_Dx (Address_000000, Data_write_D2_1, WEb_lo_D2, WEb_hi_D2)
     call Read_data (Address_000000, Data_read_D2_1)

end unit

unit   "awaretest D3 Test"

     call Write_data_Dx (Address_000000, Data_write_D3_0, WEb_lo_D3, WEb_hi_D3)
     call Read_data (Address_000000, Data_read_D3_0)

     call Write_data_Dx (Address_000000, Data_write_D3_1, WEb_lo_D3, WEb_hi_D3)
     call Read_data (Address_000000, Data_read_D3_1)

end unit

unit "RAM test"
     call Write_data (Address_000000, Data_write_0000)
     call Write_data (Address_000001, Data_write_0001)
     call Write_data (Address_000011, Data_write_0011)
     call Write_data (Address_000111, Data_write_0111)
     call Write_data (Address_001111, Data_write_1111)
     call Write_data (Address_011111, Data_write_1010)
     call Write_data (Address_111111, Data_write_0101)
     call Read_data (Address_000000, Data_read_0000)
     call Read_data (Address_000001, Data_read_0001)
     call Read_data (Address_000011, Data_read_0011)
     call Read_data (Address_000111, Data_read_0111)
     call Read_data (Address_001111, Data_read_1111)
     call Read_data (Address_011111, Data_read_1010)
     call Read_data (Address_111111, Data_read_0101)
     call Write_data (Address_000000, Data_write_1111)
     call Read_data (Address_000000, Data_read_1111)
end unit

!    End of test