!!!!    6    0    1  986750069  V1019                                         

! Device           : 6551
! Function         : Static RAM 3-state 256 x 4
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 1000n
receive delay 900n

assign    VCC            to pins   22
assign    GND            to pins   8

assign    Address        to pins   7,6,5,21,1,2,3,4
assign    Data_in        to pins   15,13,11,9
assign    Data_out       to pins   16,14,12,10

assign    Data_in_D0     to pins 9    !AT Added for minimum pin test.
assign    Data_in_D1     to pins 11   !AT Added for minimum pin test.
assign    Data_in_D2     to pins 13   !AT Added for minimum pin test.
assign    Data_in_D3     to pins 15   !AT Added for minimum pin test.

assign    Data_out_D0    to pins 10   !AT Added for minimum pin test.
assign    Data_out_D1    to pins 12   !AT Added for minimum pin test.
assign    Data_out_D2    to pins 14   !AT Added for minimum pin test.
assign    Data_out_D3    to pins 16   !AT Added for minimum pin test.

assign    Chip_enable_bar       to pins   18
assign    Chip_select_1_bar     to pins   19
assign    Chip_select_2_bar     to pins   17

assign    Write_enable_bar      to pins   20

family    TTL

power     VCC, GND

inputs    Address, Data_in, Write_enable_bar, Chip_enable_bar
inputs    Chip_select_1_bar, Chip_select_2_bar
inputs Data_in_D0, Data_in_D1, Data_in_D2, Data_in_D3      !AT Added for min pin test.

outputs   Data_out
outputs Data_out_D0, Data_out_D1, Data_out_D2, Data_out_D3 !AT Added for min pin test.

when     Write_enable_bar  is "0"   inactive Data_out
when     Chip_enable_bar   is "1"   inactive Data_out
when     Chip_select_1_bar is "1"   inactive Data_out
when     Chip_select_2_bar is "1"   inactive Data_out

trace    Data_out  to  Address, Data_in, Write_enable_bar, Chip_enable_bar
trace    Data_out  to  Chip_select_1_bar, Chip_select_2_bar

disable   Data_out  with  Chip_select_1_bar    to   "1"
disable   Data_out  with  Chip_select_2_bar    to   "1"
disable   Data_out  with  Write_enable_bar     to   "0"

!***************************************************************
!***************************************************************

vector   Disable
     set  Write_enable_bar     to   "1"
     set  Chip_enable_bar      to   "1"
     set  Chip_select_1_bar    to   "1"
     set  Chip_select_2_bar    to   "0"
end vector

vector   Chip_enable_true
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar     to   "k"
     set  Chip_enable_bar      to   "0"
     set  Chip_select_1_bar    to   "k"
     set  Chip_select_2_bar    to   "k"
end vector

vector   Write_enable_true
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar     to   "0"
     set  Chip_enable_bar      to   "k"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
end vector

vector   Write_enable_false
     set  Address              to   "kkkkkkkk"
     set  Data_in              to   "kkkk"
     set  Write_enable_bar     to   "1"
     set  Chip_enable_bar      to   "1"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
end vector

vector   Read_enable
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "k"
     set  Chip_select_1_bar   to   "0"
     set  Chip_select_2_bar   to   "1"
end vector

vector   Read_disable
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "1"
     set  Chip_select_1_bar   to   "1"
     set  Chip_select_2_bar   to   "1"
end vector

vector   Chip_select_1_false
     set  Write_enable_bar    to   "0"
     set  Chip_enable_bar     to   "K"
     set  Chip_select_1_bar   to   "1"
     set  Chip_select_2_bar   to   "K"
end vector

vector   Chip_select_2_false
     set  Write_enable_bar    to   "K"
     set  Chip_enable_bar     to   "K"
     set  Chip_select_1_bar   to   "K"
     set  Chip_select_2_bar   to   "1"
end vector

vector   Address_00000000
     initialize  to          Disable
     set  Address            to  "00000000"
     set  Chip_select_2_bar  to  "0"
end vector

vector   Address_00000001
     initialize  to          Disable
     set  Address            to  "00000001"
     set  Chip_select_2_bar  to  "0"
end vector

vector   Address_00000011
     initialize  to          Disable
     set  Address            to  "00000011"
     set  Chip_select_2_bar  to  "0"
end vector

vector   Address_00000111
     initialize  to          Disable
     set  Address            to  "00000111"
     set  Chip_select_2_bar  to  "0"
end vector

vector   Address_00001111
     initialize  to          Disable
     set  Address            to  "00001111"
     set  Chip_select_2_bar  to  "0"
end vector

vector   Address_00011111
     initialize  to          Disable
     set  Address            to  "00011111"
     set  Chip_select_2_bar  to  "0"
end vector

vector   Address_00111111
     initialize  to          Disable
     set  Address            to  "00111111"
     set  Chip_select_2_bar  to  "0"
end vector

vector   Address_01111111
     initialize  to          Disable
     set  Address            to  "01111111"
     set  Chip_select_2_bar  to  "0"
end vector

vector   Address_11111111
     initialize  to          Disable
     set  Address            to  "11111111"
     set  Chip_select_2_bar  to  "0"
end vector

vector   Data_write_0000
     initialize to  Write_enable_true
     set Data_in    to   "0000"
end vector

vector   Data_write_0001
     initialize to  Write_enable_true
     set Data_in    to   "0001"
end vector

vector   Data_write_0011
     initialize to  Write_enable_true
     set Data_in    to   "0011"
end vector

vector   Data_write_0111
     initialize to  Write_enable_true
     set Data_in    to   "0111"
end vector

vector   Data_write_1111
     initialize to  Write_enable_true
     set Data_in    to   "1111"
end vector

vector   Data_write_1110
     initialize to  Write_enable_true
     set Data_in    to   "1110"
end vector

vector   Data_write_1100
     initialize to  Write_enable_true
     set Data_in    to   "1100"
end vector

vector   Data_write_1000
     initialize to  Write_enable_true
     set Data_in    to   "1000"
end vector

vector   Data_write_1010
     initialize to  Write_enable_true
     set Data_in    to   "1010"
end vector

vector   Data_write_1111_CS_false
     set Write_enable_bar    to  "k"
     set Chip_enable_bar     to  "k"
     set Chip_select_1_bar   to  "k"
     set Chip_select_2_bar   to  "k"
     set Data_in             to  "1111"
end vector

vector   Data_read_0000
     initialize to  Read_enable
     set Data_out   to   "0000"
end vector

vector   Data_read_0001
     initialize to  Read_enable
     set Data_out   to   "0001"
end vector

vector   Data_read_0011
     initialize to  Read_enable
     set Data_out   to   "0011"
end vector

vector   Data_read_0111
     initialize to  Read_enable
     set Data_out   to   "0111"
end vector

vector   Data_read_1111
     initialize to  Read_enable
     set Data_out   to   "1111"
end vector

vector   Data_read_1110
     initialize to  Read_enable
     set Data_out   to   "1110"
end vector

vector   Data_read_1100
     initialize to  Read_enable
     set Data_out   to   "1100"
end vector

vector   Data_read_1000
     initialize to  Read_enable
     set Data_out   to   "1000"
end vector

vector   Data_read_1010
     initialize to  Read_enable
     set Data_out   to   "1010"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   Data_write_D0_0
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar     to   "0"
     set  Chip_enable_bar      to   "k"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
     set  Data_in_D0           to   "0"
end vector

vector   Data_write_D0_1
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar     to   "0"
     set  Chip_enable_bar      to   "k"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
     set  Data_in_D0           to   "1"
end vector

vector   Data_write_D1_0
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar     to   "0"
     set  Chip_enable_bar      to   "k"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
     set  Data_in_D1           to   "0"
end vector

vector   Data_write_D1_1
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar     to   "0"
     set  Chip_enable_bar      to   "k"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
     set  Data_in_D1           to   "1"
end vector

vector   Data_write_D2_0
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar     to   "0"
     set  Chip_enable_bar      to   "k"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
     set  Data_in_D2           to   "0"
end vector

vector   Data_write_D2_1
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar     to   "0"
     set  Chip_enable_bar      to   "k"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
     set  Data_in_D2           to   "1"
end vector

vector   Data_write_D3_0
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar     to   "0"
     set  Chip_enable_bar      to   "k"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
     set  Data_in_D3           to   "0"
end vector

vector   Data_write_D3_1
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar     to   "0"
     set  Chip_enable_bar      to   "k"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
     set  Data_in_D3           to   "1"
end vector

vector   Data_read_D0_0
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "k"
     set  Chip_select_1_bar   to   "0"
     set  Chip_select_2_bar   to   "1"
     set  Data_out_D0         to   "0"
end vector

vector   Data_read_D0_1
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "k"
     set  Chip_select_1_bar   to   "0"
     set  Chip_select_2_bar   to   "1"
     set  Data_out_D0         to   "1"
end vector

vector   Data_read_D1_0
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "k"
     set  Chip_select_1_bar   to   "0"
     set  Chip_select_2_bar   to   "1"
     set  Data_out_D1         to   "0"
end vector

vector   Data_read_D1_1
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "k"
     set  Chip_select_1_bar   to   "0"
     set  Chip_select_2_bar   to   "1"
     set  Data_out_D1         to   "1"
end vector

vector   Data_read_D2_0
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "k"
     set  Chip_select_1_bar   to   "0"
     set  Chip_select_2_bar   to   "1"
     set  Data_out_D2         to   "0"
end vector

vector   Data_read_D2_1
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "k"
     set  Chip_select_1_bar   to   "0"
     set  Chip_select_2_bar   to   "1"
     set  Data_out_D2         to   "1"
end vector

vector   Data_read_D3_0
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "k"
     set  Chip_select_1_bar   to   "0"
     set  Chip_select_2_bar   to   "1"
     set  Data_out_D3         to   "0"
end vector

vector   Data_read_D3_1
     set  Address              to   "kkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "k"
     set  Chip_select_1_bar   to   "0"
     set  Chip_select_2_bar   to   "1"
     set  Data_out_D3         to   "1"
end vector

vector   WEb_hi_D0
     set  Address              to   "kkkkkkkk"
     set  Data_in_D0           to   "k"
     set  Write_enable_bar     to   "1"
     set  Chip_enable_bar      to   "1"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
end vector

vector   WEb_hi_D1
     set  Address              to   "kkkkkkkk"
     set  Data_in_D1           to   "k"
     set  Write_enable_bar     to   "1"
     set  Chip_enable_bar      to   "1"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
end vector

vector   WEb_hi_D2
     set  Address              to   "kkkkkkkk"
     set  Data_in_D2           to   "k"
     set  Write_enable_bar     to   "1"
     set  Chip_enable_bar      to   "1"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
end vector

vector   WEb_hi_D3
     set  Address              to   "kkkkkkkk"
     set  Data_in_D3           to   "k"
     set  Write_enable_bar     to   "1"
     set  Chip_enable_bar      to   "1"
     set  Chip_select_1_bar    to   "0"
     set  Chip_select_2_bar    to   "1"
end vector

!***************************************************************
!***************************************************************

sub  Write_data (Address, Data)
     execute   Address
     execute   Chip_enable_true
     execute   Data
     execute   Write_enable_false
end sub

sub  Read_data (Address, Data)
     execute   Address
     execute   Chip_enable_true
     execute   Data
     execute   Read_disable
end sub

!***************************************************************

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, WEb_hi_Dx)
     execute   Address
     execute   Chip_enable_true
     execute   Data_Dx
     execute   WEb_hi_Dx
end sub

!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

    call Write_data_Dx (Address_00000000,Data_write_D0_0, WEb_hi_D0)
    call Read_data (Address_00000000,Data_read_D0_0)

    call Write_data_Dx (Address_00000000,Data_write_D0_1, WEb_hi_D0)
    call Read_data (Address_00000000,Data_read_D0_1)

end unit

unit   "awaretest D1 Test"

    call Write_data_Dx (Address_00000000,Data_write_D1_0, WEb_hi_D1)
    call Read_data (Address_00000000,Data_read_D1_0)

    call Write_data_Dx (Address_00000000,Data_write_D1_1, WEb_hi_D1)
    call Read_data (Address_00000000,Data_read_D1_1)

end unit

unit   "awaretest D2 Test"

    call Write_data_Dx (Address_00000000,Data_write_D2_0, WEb_hi_D2)
    call Read_data (Address_00000000,Data_read_D2_0)

    call Write_data_Dx (Address_00000000,Data_write_D2_1, WEb_hi_D2)
    call Read_data (Address_00000000,Data_read_D2_1)

end unit

unit   "awaretest D3 Test"

    call Write_data_Dx (Address_00000000,Data_write_D3_0, WEb_hi_D3)
    call Read_data (Address_00000000,Data_read_D3_0)

    call Write_data_Dx (Address_00000000,Data_write_D3_1, WEb_hi_D3)
    call Read_data (Address_00000000,Data_read_D3_1)

end unit

unit "RAM test"
     call Write_data (Address_00000000, Data_write_0000)
     call Write_data (Address_00000001, Data_write_0001)
     call Write_data (Address_00000011, Data_write_0011)
     call Write_data (Address_00000111, Data_write_0111)
     call Write_data (Address_00001111, Data_write_1111)
     call Write_data (Address_00011111, Data_write_1110)
     call Write_data (Address_00111111, Data_write_1100)
     call Write_data (Address_01111111, Data_write_1000)
     call Write_data (Address_11111111, Data_write_1010)
     call Read_data (Address_00000000, Data_read_0000)
     call Read_data (Address_00000001, Data_read_0001)
     call Read_data (Address_00000011, Data_read_0011)
     call Read_data (Address_00000111, Data_read_0111)
     call Read_data (Address_00001111, Data_read_1111)
     call Read_data (Address_00011111, Data_read_1110)
     call Read_data (Address_00111111, Data_read_1100)
     call Read_data (Address_01111111, Data_read_1000)
     call Read_data (Address_11111111, Data_read_1010)
end unit

unit "Test Chip_enable_1_false"
     call Write_data (Address_00000000, Data_write_0000)
     execute Address_00000000
     execute Chip_enable_true
     execute Chip_select_1_false
     execute Data_write_1111_CS_false
     execute Write_enable_false
     call Read_data (Address_00000000, Data_read_0000)
end unit

unit "Test Chip_enable_2_false"
     call Write_data (Address_00000000, Data_write_0000)
     execute Address_00000000
     execute Chip_select_2_false
     execute Chip_enable_true
     execute Write_enable_true
     execute Data_write_1111
     execute Write_enable_false
     call Read_data (Address_00000000, Data_read_0000)
end unit

!    End of test