!!!!    6    0    1  987108239  Vb4b3                                         

! Device           : 6516
! Function         : Static RAM 2048 x 8    CMOS
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

warning "Pull-ups are required to test high impedance outputs."

assign       VCC                 to pins           24
assign       GND                 to pins           12

assign       Address_bus         to pins           19,22,23,1,2,3
assign       Address_bus         to pins 4,5,6,7,8
assign       Data_bus            to pins           17,16,15,14,13
assign       Data_bus            to pins 11,10,9
assign       Data_D0             to pins   9    !AT Added for minimum pin test.
assign       Data_D1             to pins   10   !AT Added for minimum pin test.
assign       Data_D2             to pins   11   !AT Added for minimum pin test.
assign       Data_D3             to pins   13   !AT Added for minimum pin test.
assign       Data_D4             to pins   14   !AT Added for minimum pin test.
assign       Data_D5             to pins   15   !AT Added for minimum pin test.
assign       Data_D6             to pins   16   !AT Added for minimum pin test.
assign       Data_D7             to pins   17   !AT Added for minimum pin test.

assign       Chip_Enable_bar     to pins           18
assign       Output_Enable_bar   to pins           20
assign       Write_bar           to pins           21

family       TTL

power        VCC, GND

inputs       Address_bus, Chip_Enable_bar, Output_Enable_bar, Write_bar

bidirectional       Data_bus
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.
bidirectional  Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test.

when     Chip_enable_bar   is "1"   inactive Data_bus
when     Output_enable_bar is "1"   inactive Data_bus
when     Write_bar         is "1"   outputs  Data_bus
when     Write_bar         is "0"   inputs   Data_bus

trace    Data_bus to  Address_bus,Chip_Enable_bar,Output_Enable_bar,Write_bar

disable      Data_bus   with   Chip_Enable_bar   to    "1"
disable      Data_bus   with   Output_Enable_bar to    "1"

set load on groups Data_bus to pull up
!*****************************************************************************
!*****************************************************************************

vector       Disable_chip
     set     Chip_Enable_bar      to         "1"
     set     Output_Enable_bar    to         "1"
     set     Write_bar            to         "1"
end vector

vector       Write_enable
     set     Chip_Enable_bar      to         "0"
     set     Output_Enable_bar    to         "1"
     set     Write_bar            to         "0"
     set     Address_bus          to         "kkkkkkkkkkk"
end vector

vector       Chip_Enable_true
     set     Chip_Enable_bar      to         "0"
     set     Output_Enable_bar    to         "1"
     set     Write_bar            to         "1"
     set     Address_bus          to         "kkkkkkkkkkk"
end vector

vector       Read_enable
     set     Chip_Enable_bar      to         "0"
     set     Output_Enable_bar    to         "0"
     set     Write_bar            to         "1"
     set     Address_bus          to         "kkkkkkkkkkk"
end vector

vector       Write_false
     initialize to Chip_Enable_true
     drive Data_bus
     set     Data_bus             to         "kkkkkkkk"
end vector

vector       Chip_Enable_false
     set     Chip_Enable_bar      to         "1"
     set     Output_Enable_bar    to         "1"
     set     Write_bar            to         "0"
     set     Address_bus          to         "kkkkkkkkkkk"
end vector

vector       Write_disable
     initialize to Disable_chip
     drive   Data_bus
     set     Address_bus          to         "kkkkkkkkkkk"
     set     Data_bus             to         "kkkkkkkk"
end vector

vector       Write_11111111
     initialize to Chip_Enable_false
     drive Data_bus
     set     Data_bus             to         "11111111"
end vector

vector       Write_00000000
     initialize to Chip_Enable_true
     drive Data_bus
     set     Data_bus             to         "00000000"
end vector

vector       Read_11111111
     initialize to Chip_Enable_true
     receive Data_bus
     set     Data_bus             to         "11111111"
end vector

vector       Address_00000000000
     initialize to Disable_chip
     set     Address_bus          to         "00000000000"
end vector

vector       Address_00000000001
     initialize to Disable_chip
     set     Address_bus          to         "00000000001"
end vector

vector       Address_00000000011
     initialize to Disable_chip
     set     Address_bus          to         "00000000011"
end vector

vector       Address_00000000111
     initialize to Disable_chip
     set     Address_bus          to         "00000000111"
end vector

vector       Address_00000001111
     initialize to Disable_chip
     set     Address_bus          to         "00000001111"
end vector

vector       Address_00000011111
     initialize to Disable_chip
     set     Address_bus          to         "00000011111"
end vector

vector       Address_00000111111
     initialize to Disable_chip
     set     Address_bus          to         "00000111111"
end vector

vector       Address_00001111111
     initialize to Disable_chip
     set     Address_bus          to         "00001111111"
end vector

vector       Address_00011111111
     initialize to Disable_chip
     set     Address_bus          to         "00011111111"
end vector

vector       Address_00111111111
     initialize to Disable_chip
     set     Address_bus          to         "00111111111"
end vector

vector       Address_01111111111
     initialize to Disable_chip
     set     Address_bus          to         "01111111111"
end vector

vector       Address_11111111111
     initialize to Disable_chip
     set     Address_bus          to         "11111111111"
end vector

vector       Data_In_00000000
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "00000000"
end vector

vector       Data_In_00000001
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "00000001"
end vector

vector       Data_In_00000011
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "00000011"
end vector

vector       Data_In_00000111
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "00000111"
end vector

vector       Data_In_00001111
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "00001111"
end vector

vector       Data_In_00011111
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "00011111"
end vector

vector       Data_In_00111111
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "00111111"
end vector

vector       Data_In_01111111
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "01111111"
end vector

vector       Data_In_11111111
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "11111111"
end vector

vector       Data_In_11111110
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "11111110"
end vector

vector       Data_In_11111100
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "11111100"
end vector

vector       Data_In_11111000
     initialize to Write_enable
     drive Data_bus
     set     Data_bus             to         "11111000"
end vector

vector       Data_Out_00000000
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "00000000"
end vector

vector       Data_Out_00000001
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "00000001"
end vector

vector       Data_Out_00000011
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "00000011"
end vector

vector       Data_Out_00000111
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "00000111"
end vector

vector       Data_Out_00001111
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "00001111"
end vector

vector       Data_Out_00011111
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "00011111"
end vector

vector       Data_Out_00111111
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "00111111"
end vector

vector       Data_Out_01111111
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "01111111"
end vector

vector       Data_Out_11111111
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "11111111"
end vector

vector       Data_Out_11111110
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "11111110"
end vector

vector       Data_Out_11111100
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "11111100"
end vector

vector       Data_Out_11111000
     initialize to Read_enable
     receive Data_bus
     set     Data_bus             to         "11111000"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector       Write_false_D0
     initialize to Chip_Enable_true
     drive Data_D0
     set     Data_D0              to         "k"
end vector

vector       Write_false_D1
     initialize to Chip_Enable_true
     drive Data_D1
     set     Data_D1              to         "k"
end vector

vector       Write_false_D2
     initialize to Chip_Enable_true
     drive Data_D2
     set     Data_D2              to         "k"
end vector

vector       Write_false_D3
     initialize to Chip_Enable_true
     drive Data_D3
     set     Data_D3              to         "k"
end vector

vector       Write_false_D4
     initialize to Chip_Enable_true
     drive Data_D4
     set     Data_D4              to         "k"
end vector

vector       Write_false_D5
     initialize to Chip_Enable_true
     drive Data_D5
     set     Data_D5              to         "k"
end vector

vector       Write_false_D6
     initialize to Chip_Enable_true
     drive Data_D6
     set     Data_D6              to         "k"
end vector

vector       Write_false_D7
     initialize to Chip_Enable_true
     drive Data_D7
     set     Data_D7              to         "k"
end vector

vector       Data_In_D0_0
     initialize to Write_enable
     drive Data_D0
     set     Data_D0              to         "0"
end vector

vector       Data_In_D0_1
     initialize to Write_enable
     drive Data_D0
     set     Data_D0              to         "1"
end vector

vector       Data_In_D1_0
     initialize to Write_enable
     drive Data_D1
     set     Data_D1              to         "0"
end vector

vector       Data_In_D1_1
     initialize to Write_enable
     drive Data_D1
     set     Data_D1              to         "1"
end vector

vector       Data_In_D2_0
     initialize to Write_enable
     drive Data_D2
     set     Data_D2              to         "0"
end vector

vector       Data_In_D2_1
     initialize to Write_enable
     drive Data_D2
     set     Data_D2              to         "1"
end vector

vector       Data_In_D3_0
     initialize to Write_enable
     drive Data_D3
     set     Data_D3              to         "0"
end vector

vector       Data_In_D3_1
     initialize to Write_enable
     drive Data_D3
     set     Data_D3              to         "1"
end vector

vector       Data_In_D4_0
     initialize to Write_enable
     drive Data_D4
     set     Data_D4              to         "0"
end vector

vector       Data_In_D4_1
     initialize to Write_enable
     drive Data_D4
     set     Data_D4              to         "1"
end vector

vector       Data_In_D5_0
     initialize to Write_enable
     drive Data_D5
     set     Data_D5              to         "0"
end vector

vector       Data_In_D5_1
     initialize to Write_enable
     drive Data_D5
     set     Data_D5              to         "1"
end vector

vector       Data_In_D6_0
     initialize to Write_enable
     drive Data_D6
     set     Data_D6              to         "0"
end vector

vector       Data_In_D6_1
     initialize to Write_enable
     drive Data_D6
     set     Data_D6              to         "1"
end vector

vector       Data_In_D7_0
     initialize to Write_enable
     drive Data_D7
     set     Data_D7              to         "0"
end vector

vector       Data_In_D7_1
     initialize to Write_enable
     drive Data_D7
     set     Data_D7              to         "1"
end vector

vector       Data_Out_D0_0
     initialize to Read_enable
     receive Data_D0
     set     Data_D0              to         "0"
end vector

vector       Data_Out_D0_1
     initialize to Read_enable
     receive Data_D0
     set     Data_D0              to         "1"
end vector

vector       Data_Out_D1_0
     initialize to Read_enable
     receive Data_D1
     set     Data_D1              to         "0"
end vector

vector       Data_Out_D1_1
     initialize to Read_enable
     receive Data_D1
     set     Data_D1              to         "1"
end vector

vector       Data_Out_D2_0
     initialize to Read_enable
     receive Data_D2
     set     Data_D2              to         "0"
end vector

vector       Data_Out_D2_1
     initialize to Read_enable
     receive Data_D2
     set     Data_D2              to         "1"
end vector

vector       Data_Out_D3_0
     initialize to Read_enable
     receive Data_D3
     set     Data_D3              to         "0"
end vector

vector       Data_Out_D3_1
     initialize to Read_enable
     receive Data_D3
     set     Data_D3              to         "1"
end vector

vector       Data_Out_D4_0
     initialize to Read_enable
     receive Data_D4
     set     Data_D4              to         "0"
end vector

vector       Data_Out_D4_1
     initialize to Read_enable
     receive Data_D4
     set     Data_D4              to         "1"
end vector

vector       Data_Out_D5_0
     initialize to Read_enable
     receive Data_D5
     set     Data_D5              to         "0"
end vector

vector       Data_Out_D5_1
     initialize to Read_enable
     receive Data_D5
     set     Data_D5              to         "1"
end vector

vector       Data_Out_D6_0
     initialize to Read_enable
     receive Data_D6
     set     Data_D6              to         "0"
end vector

vector       Data_Out_D6_1
     initialize to Read_enable
     receive Data_D6
     set     Data_D6              to         "1"
end vector

vector       Data_Out_D7_0
     initialize to Read_enable
     receive Data_D7
     set     Data_D7              to         "0"
end vector

vector       Data_Out_D7_1
     initialize to Read_enable
     receive Data_D7
     set     Data_D7              to         "1"
end vector

!*****************************************************************************
!*****************************************************************************

! "Ram_Test" tests I/O pins for proper operation using a graycode
! pattern for both addresses and data.
! "Test_Chip_Enable_bar" tests for proper operation of the E_bar pin
! "Test_Write_bar" tests for proper operation of the W_bar pin

sub  Write_Data (Address,Data)
      execute              Address
      execute              Chip_Enable_true
      execute              Data
      execute              Write_false
      execute              Disable_chip
end sub

sub  Read_Data (Address,Data)
      execute              Address
      execute              Chip_Enable_true
      execute              Read_enable
      execute              Data
      execute              Disable_chip
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, Write_false_Dx)
      execute              Address
      execute              Chip_Enable_true
      execute              Data_Dx
      execute              Write_false_Dx
      execute              Disable_chip
end sub

!*****************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

      call   Write_Data_Dx (Address_00000000000, Data_In_D0_0, Write_false_D0)
      call   Read_Data (Address_00000000000, Data_Out_D0_0)

      call   Write_Data_Dx (Address_00000000000, Data_In_D0_1, Write_false_D0)
      call   Read_Data (Address_00000000000, Data_Out_D0_1)

end unit

unit   "awaretest D1 Test"

      call   Write_Data_Dx (Address_00000000000, Data_In_D1_0, Write_false_D1)
      call   Read_Data (Address_00000000000, Data_Out_D1_0)

      call   Write_Data_Dx (Address_00000000000, Data_In_D1_1, Write_false_D1)
      call   Read_Data (Address_00000000000, Data_Out_D1_1)

end unit

unit   "awaretest D2 Test"

      call   Write_Data_Dx (Address_00000000000, Data_In_D2_0, Write_false_D2)
      call   Read_Data (Address_00000000000, Data_Out_D2_0)

      call   Write_Data_Dx (Address_00000000000, Data_In_D2_1, Write_false_D2)
      call   Read_Data (Address_00000000000, Data_Out_D2_1)

end unit

unit   "awaretest D3 Test"

      call   Write_Data_Dx (Address_00000000000, Data_In_D3_0, Write_false_D3)
      call   Read_Data (Address_00000000000, Data_Out_D3_0)

      call   Write_Data_Dx (Address_00000000000, Data_In_D3_1, Write_false_D3)
      call   Read_Data (Address_00000000000, Data_Out_D3_1)

end unit

unit   "awaretest D4 Test"

      call   Write_Data_Dx (Address_00000000000, Data_In_D4_0, Write_false_D4)
      call   Read_Data (Address_00000000000, Data_Out_D4_0)

      call   Write_Data_Dx (Address_00000000000, Data_In_D4_1, Write_false_D4)
      call   Read_Data (Address_00000000000, Data_Out_D4_1)

end unit

unit   "awaretest D5 Test"

      call   Write_Data_Dx (Address_00000000000, Data_In_D5_0, Write_false_D5)
      call   Read_Data (Address_00000000000, Data_Out_D5_0)

      call   Write_Data_Dx (Address_00000000000, Data_In_D5_1, Write_false_D5)
      call   Read_Data (Address_00000000000, Data_Out_D5_1)

end unit

unit   "awaretest D6 Test"

      call   Write_Data_Dx (Address_00000000000, Data_In_D6_0, Write_false_D6)
      call   Read_Data (Address_00000000000, Data_Out_D6_0)

      call   Write_Data_Dx (Address_00000000000, Data_In_D6_1, Write_false_D6)
      call   Read_Data (Address_00000000000, Data_Out_D6_1)

end unit

unit   "awaretest D7 Test"

      call   Write_Data_Dx (Address_00000000000, Data_In_D7_0, Write_false_D7)
      call   Read_Data (Address_00000000000, Data_Out_D7_0)

      call   Write_Data_Dx (Address_00000000000, Data_In_D7_1, Write_false_D7)
      call   Read_Data (Address_00000000000, Data_Out_D7_1)

end unit

unit    "Ram_Test"
      call      Write_Data (Address_00000000000,Data_In_00000000)
      call      Write_Data (Address_00000000001,Data_In_00000001)
      call      Write_Data (Address_00000000011,Data_In_00000011)
      call      Write_Data (Address_00000000111,Data_In_00000111)
      call      Write_Data (Address_00000001111,Data_In_00001111)
      call      Write_Data (Address_00000011111,Data_In_00011111)
      call      Write_Data (Address_00000111111,Data_In_00111111)
      call      Write_Data (Address_00001111111,Data_In_01111111)
      call      Write_Data (Address_00011111111,Data_In_11111111)
      call      Write_Data (Address_00111111111,Data_In_11111110)
      call      Write_Data (Address_01111111111,Data_In_11111100)
      call      Write_Data (Address_11111111111,Data_In_11111000)

      call      Read_Data (Address_00000000000,Data_Out_00000000)
      call      Read_Data (Address_00000000001,Data_Out_00000001)
      call      Read_Data (Address_00000000011,Data_Out_00000011)
      call      Read_Data (Address_00000000111,Data_Out_00000111)
      call      Read_Data (Address_00000001111,Data_Out_00001111)
      call      Read_Data (Address_00000011111,Data_Out_00011111)
      call      Read_Data (Address_00000111111,Data_Out_00111111)
      call      Read_Data (Address_00001111111,Data_Out_01111111)
      call      Read_Data (Address_00011111111,Data_Out_11111111)
      call      Read_Data (Address_00111111111,Data_Out_11111110)
      call      Read_Data (Address_01111111111,Data_Out_11111100)
      call      Read_Data (Address_11111111111,Data_Out_11111000)
      call      Write_Data (Address_00000000001,Data_In_11111111)
end unit

unit      "Test_Chip_Enable_bar"
      call           Write_Data (Address_00000000000,Data_In_00000000)
      execute        Address_00000000000
      execute        Chip_Enable_false
      execute        Write_11111111
      execute        Write_disable
      execute        Disable_chip
      call           Read_Data (Address_00000000000,Data_Out_00000000)
end unit

unit     "Test Write_bar"
      call           Write_Data (Address_00000000000,Data_In_11111111)
      execute        Address_00000000000
      execute        Chip_Enable_true
      execute        Write_00000000
      execute        Write_false
      execute        Disable_chip
      call           Read_Data (Address_00000000000,Data_Out_11111111)
end unit

 unit     "Test Output_enable_bar"
       call           Write_Data (Address_00000000000,Data_In_00000000)
       execute        Address_00000000000
       execute        Chip_Enable_true
       execute        Chip_Enable_true
       execute        Read_11111111
       execute        Disable_chip
 end unit

!     End of test