!!!!    6    0    1  986770428  Vdc2f                                         

! Device           : 5517
! Function         : Static RAM 2048 x 8    CMOS
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle  400n
receive delay 300n

warning "Pull-ups are required to test high-impedance outputs."

assign    VCC            to pins   24
assign    GND            to pins   12

assign    Address_Bus    to pins   19,22,23,1,2,3,4,5,6,7
assign    Address_Bus    to pins 8

assign    Data_Bus       to pins   17,16,15,14,13,11,10,9
assign    Data_D0        to pins   9    !AT Added for minimum pin test.
assign    Data_D1        to pins   10   !AT Added for minimum pin test.
assign    Data_D2        to pins   11   !AT Added for minimum pin test.
assign    Data_D3        to pins   13   !AT Added for minimum pin test.
assign    Data_D4        to pins   14   !AT Added for minimum pin test.
assign    Data_D5        to pins   15   !AT Added for minimum pin test.
assign    Data_D6        to pins   16   !AT Added for minimum pin test.
assign    Data_D7        to pins   17   !AT Added for minimum pin test.

assign    Chip_Enable         to pins   18
assign    Chip_Write_Enable   to pins   21
assign    Chip_Output_Enable  to pins   20

family    TTL

power          VCC, GND

inputs         Address_Bus,Chip_Output_Enable,Chip_Enable,Chip_Write_Enable

bidirectional  Data_Bus
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.
bidirectional  Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test.

when     Chip_enable    is    "1"   inactive Data_bus
when     Chip_output_enable is "1"   inactive Data_bus
when     Chip_write_enable is    "1"   outputs  Data_bus
when     Chip_write_enable is    "0"   inputs   Data_bus

trace    Data_bus  to  Address_Bus,Chip_Output_Enable
trace    Data_bus  to  Chip_Enable,Chip_Write_Enable

disable   Data_Bus  with Chip_enable         to   "1"
disable   Data_Bus  with Chip_Output_Enable  to   "1"

set load on groups Data_Bus to pull up
!***************************************************************
!***************************************************************

vector   Output_enable_false
   set   Chip_output_enable   to "1"
   set   Chip_write_enable    to "k"
   set   Chip_enable          to "k"
end   vector

vector   Chip_enable_true
   set   Chip_output_enable   to "k"
   set   Chip_write_enable    to "k"
   set   Chip_enable          to "0"
   set   Address_Bus          to "kkkkkkkkkkk"
end   vector

vector    Read_enable
   set  Address_Bus         to   "kkkkkkkkkkk"
   set  Chip_Output_Enable  to   "k"
   set  Chip_Write_Enable   to   "1"
   set  Chip_Enable         to   "k"
end vector

vector    Write_enable
   set  Address_Bus         to   "kkkkkkkkkkk"
   set  Chip_Output_Enable  to   "k"
   set  Chip_Write_Enable   to   "0"
   set  Chip_Enable         to   "k"
end vector

vector    Write_enable_CS_false
   set  Address_Bus         to   "kkkkkkkkkkk"
   set  Chip_Output_Enable  to   "k"
   set  Chip_Write_Enable   to   "0"
   set  Chip_Enable         to   "1"
end vector

vector    Disable
   set  Chip_Output_Enable  to   "0"
   set  Chip_Write_Enable   to   "1"
   set  Chip_Enable         to   "1"
end vector

vector    Address_00000000000
   initialize to  Chip_enable_true
   set  Address_Bus   to   "00000000000"
end vector

vector    Address_00000000001
   initialize to  Chip_enable_true
   set  Address_Bus   to   "00000000001"
end vector

vector    Address_00000000011
   initialize to  Chip_enable_true
   set  Address_Bus   to   "00000000011"
end vector

vector    Address_00000000111
   initialize to  Chip_enable_true
   set  Address_Bus   to   "00000000111"
end vector

vector    Address_00000001111
   initialize to  Chip_enable_true
   set  Address_Bus   to   "00000001111"
end vector

vector    Address_00000011111
   initialize to  Chip_enable_true
   set  Address_Bus   to   "00000011111"
end vector

vector    Address_00000111111
   initialize to  Chip_enable_true
   set  Address_Bus   to   "00000111111"
end vector

vector    Address_00001111111
   initialize to  Chip_enable_true
   set  Address_Bus   to   "00001111111"
end vector

vector    Address_00011111111
   initialize to  Chip_enable_true
   set  Address_Bus   to   "00011111111"
end vector

vector    Address_00111111111
   initialize to  Chip_enable_true
   set  Address_Bus   to   "00111111111"
end vector

vector    Address_01111111111
   initialize to  Chip_enable_true
   set  Address_Bus   to   "01111111111"
end vector

vector    Address_11111111111
   initialize to Chip_enable_true
   set  Address_Bus   to   "11111111111"
end vector

vector    Data_write_10101010_CS_false
   drive     Data_Bus
   set  Address_Bus             to   "kkkkkkkkkkk"
   set  Data_Bus                to   "10101010"
   set  Chip_Enable         to   "1"
   set  Chip_Write_Enable   to   "0"
   set  Chip_Output_Enable  to   "1"
end vector

vector    Data_write_00000000
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "00000000"
end vector

vector    Data_write_00010001
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "00010001"
end vector

vector    Data_write_00110011
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "00110011"
end vector

vector    Data_write_01110111
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "01110111"
end vector

vector    Data_write_11111111
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "11111111"
end vector

vector    Data_write_11100111
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "11100111"
end vector

vector    Data_write_11000011
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "11000011"
end vector

vector    Data_write_10000001
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "10000001"
end vector

vector    Data_write_10100101
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "10100101"
end vector

vector    Data_write_00100100
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "00100100"
end vector

vector    Data_write_01100110
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "01100110"
end vector

vector    Data_write_01011010
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "01011010"
end vector

vector    Data_write_11011011
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "11011011"
end vector

vector    Data_write_10011001
   initialize to  Write_enable
   drive     Data_Bus
   set Data_Bus       to   "10011001"
end vector

vector    Data_read_00000000
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "00000000"
end vector

vector    Data_read_00010001
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "00010001"
end vector

vector    Data_read_00110011
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "00110011"
end vector

vector    Data_read_01110111
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "01110111"
end vector

vector    Data_read_11111111
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "11111111"
end vector

vector    Data_read_11100111
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "11100111"
end vector

vector    Data_read_11000011
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "11000011"
end vector

vector    Data_read_10000001
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "10000001"
end vector

vector    Data_read_10100101
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "10100101"
end vector

vector    Data_read_00100100
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "00100100"
end vector

vector    Data_read_01100110
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "01100110"
end vector

vector    Data_read_01011010
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "01011010"
end vector

vector    Data_read_11011011
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "11011011"
end vector

vector    Data_read_10011001
   initialize to  Read_enable
   receive   Data_Bus
   set Data_Bus       to   "10011001"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Data_write_D0_0
   initialize to  Write_enable
   drive     Data_D0
   set Data_D0        to   "0"
end vector

vector    Data_write_D0_1
   initialize to  Write_enable
   drive     Data_D0
   set Data_D0        to   "1"
end vector

vector    Data_write_D1_0
   initialize to  Write_enable
   drive     Data_D1
   set Data_D1        to   "0"
end vector

vector    Data_write_D1_1
   initialize to  Write_enable
   drive     Data_D1
   set Data_D1        to   "1"
end vector

vector    Data_write_D2_0
   initialize to  Write_enable
   drive     Data_D2
   set Data_D2        to   "0"
end vector

vector    Data_write_D2_1
   initialize to  Write_enable
   drive     Data_D2
   set Data_D2        to   "1"
end vector

vector    Data_write_D3_0
   initialize to  Write_enable
   drive     Data_D3
   set Data_D3        to   "0"
end vector

vector    Data_write_D3_1
   initialize to  Write_enable
   drive     Data_D3
   set Data_D3        to   "1"
end vector

vector    Data_write_D4_0
   initialize to  Write_enable
   drive     Data_D4
   set Data_D4        to   "0"
end vector

vector    Data_write_D4_1
   initialize to  Write_enable
   drive     Data_D4
   set Data_D4        to   "1"
end vector

vector    Data_write_D5_0
   initialize to  Write_enable
   drive     Data_D5
   set Data_D5        to   "0"
end vector

vector    Data_write_D5_1
   initialize to  Write_enable
   drive     Data_D5
   set Data_D5        to   "1"
end vector

vector    Data_write_D6_0
   initialize to  Write_enable
   drive     Data_D6
   set Data_D6        to   "0"
end vector

vector    Data_write_D6_1
   initialize to  Write_enable
   drive     Data_D6
   set Data_D6        to   "1"
end vector

vector    Data_write_D7_0
   initialize to  Write_enable
   drive     Data_D7
   set Data_D7        to   "0"
end vector

vector    Data_write_D7_1
   initialize to  Write_enable
   drive     Data_D7
   set Data_D7        to   "1"
end vector

vector    Data_read_D0_0
   initialize to  Read_enable
   receive   Data_D0
   set Data_D0        to   "0"
end vector

vector    Data_read_D0_1
   initialize to  Read_enable
   receive   Data_D0
   set Data_D0        to   "1"
end vector

vector    Data_read_D1_0
   initialize to  Read_enable
   receive   Data_D1
   set Data_D1        to   "0"
end vector

vector    Data_read_D1_1
   initialize to  Read_enable
   receive   Data_D1
   set Data_D1        to   "1"
end vector

vector    Data_read_D2_0
   initialize to  Read_enable
   receive   Data_D2
   set Data_D2        to   "0"
end vector

vector    Data_read_D2_1
   initialize to  Read_enable
   receive   Data_D2
   set Data_D2        to   "1"
end vector

vector    Data_read_D3_0
   initialize to  Read_enable
   receive   Data_D3
   set Data_D3        to   "0"
end vector

vector    Data_read_D3_1
   initialize to  Read_enable
   receive   Data_D3
   set Data_D3        to   "1"
end vector

vector    Data_read_D4_0
   initialize to  Read_enable
   receive   Data_D4
   set Data_D4        to   "0"
end vector

vector    Data_read_D4_1
   initialize to  Read_enable
   receive   Data_D4
   set Data_D4        to   "1"
end vector

vector    Data_read_D5_0
   initialize to  Read_enable
   receive   Data_D5
   set Data_D5        to   "0"
end vector

vector    Data_read_D5_1
   initialize to  Read_enable
   receive   Data_D5
   set Data_D5        to   "1"
end vector

vector    Data_read_D6_0
   initialize to  Read_enable
   receive   Data_D6
   set Data_D6        to   "0"
end vector

vector    Data_read_D6_1
   initialize to  Read_enable
   receive   Data_D6
   set Data_D6        to   "1"
end vector

vector    Data_read_D7_0
   initialize to  Read_enable
   receive   Data_D7
   set Data_D7        to   "0"
end vector

vector    Data_read_D7_1
   initialize to  Read_enable
   receive   Data_D7
   set Data_D7        to   "1"
end vector

!***************************************************************
!***************************************************************

sub  Write_data (Address_Bus, Data_Bus)
   execute   Address_Bus
   execute   Data_Bus
   execute   Disable
end sub

sub  Read_data (Address_Bus, Data_Bus)
   execute   Address_Bus
   execute   Data_Bus
end sub

!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

   execute  Disable

   call Write_data (Address_00000000000, Data_write_D0_0)
   call Read_data (Address_00000000000, Data_read_D0_0)

   call Write_data (Address_00000000000, Data_write_D0_1)
   call Read_data (Address_00000000000, Data_read_D0_1)

end unit

unit   "awaretest D1 Test"

   execute  Disable

   call Write_data (Address_00000000000, Data_write_D1_0)
   call Read_data (Address_00000000000, Data_read_D1_0)

   call Write_data (Address_00000000000, Data_write_D1_1)
   call Read_data (Address_00000000000, Data_read_D1_1)

end unit

unit   "awaretest D2 Test"

   execute  Disable

   call Write_data (Address_00000000000, Data_write_D2_0)
   call Read_data (Address_00000000000, Data_read_D2_0)

   call Write_data (Address_00000000000, Data_write_D2_1)
   call Read_data (Address_00000000000, Data_read_D2_1)

end unit

unit   "awaretest D3 Test"

   execute  Disable

   call Write_data (Address_00000000000, Data_write_D3_0)
   call Read_data (Address_00000000000, Data_read_D3_0)

   call Write_data (Address_00000000000, Data_write_D3_1)
   call Read_data (Address_00000000000, Data_read_D3_1)

end unit

unit   "awaretest D4 Test"

   execute  Disable

   call Write_data (Address_00000000000, Data_write_D4_0)
   call Read_data (Address_00000000000, Data_read_D4_0)

   call Write_data (Address_00000000000, Data_write_D4_1)
   call Read_data (Address_00000000000, Data_read_D4_1)

end unit

unit   "awaretest D5 Test"

   execute  Disable

   call Write_data (Address_00000000000, Data_write_D5_0)
   call Read_data (Address_00000000000, Data_read_D5_0)

   call Write_data (Address_00000000000, Data_write_D5_1)
   call Read_data (Address_00000000000, Data_read_D5_1)

end unit

unit   "awaretest D6 Test"

   execute  Disable

   call Write_data (Address_00000000000, Data_write_D6_0)
   call Read_data (Address_00000000000, Data_read_D6_0)

   call Write_data (Address_00000000000, Data_write_D6_1)
   call Read_data (Address_00000000000, Data_read_D6_1)

end unit

unit   "awaretest D7 Test"

   execute  Disable

   call Write_data (Address_00000000000, Data_write_D7_0)
   call Read_data (Address_00000000000, Data_read_D7_0)

   call Write_data (Address_00000000000, Data_write_D7_1)
   call Read_data (Address_00000000000, Data_read_D7_1)

end unit

unit "RAM test"
   execute  Disable

   call Write_data (Address_00000000000, Data_write_00000000)
   call Write_data (Address_00000000001, Data_write_00010001)
   call Write_data (Address_00000000011, Data_write_00110011)
   call Write_data (Address_00000000111, Data_write_01110111)
   call Write_data (Address_00000001111, Data_write_11111111)
   call Write_data (Address_00000011111, Data_write_11100111)
   call Write_data (Address_00000111111, Data_write_11000011)
   call Write_data (Address_00001111111, Data_write_10000001)
   call Write_data (Address_00011111111, Data_write_10100101)
   call Write_data (Address_00111111111, Data_write_00100100)
   call Write_data (Address_01111111111, Data_write_01100110)
   call Write_data (Address_11111111111, Data_write_01011010)

   call Read_data (Address_00000000000, Data_read_00000000)
   call Read_data (Address_00000000001, Data_read_00010001)
   call Read_data (Address_00000000011, Data_read_00110011)
   call Read_data (Address_00000000111, Data_read_01110111)
   call Read_data (Address_00000001111, Data_read_11111111)
   call Read_data (Address_00000011111, Data_read_11100111)
   call Read_data (Address_00000111111, Data_read_11000011)
   call Read_data (Address_00001111111, Data_read_10000001)
   call Read_data (Address_00011111111, Data_read_10100101)
   call Read_data (Address_00111111111, Data_read_00100100)
   call Read_data (Address_01111111111, Data_read_01100110)
   call Read_data (Address_11111111111, Data_read_01011010)

   call Write_data (Address_00000000000, Data_write_11111111)
   call Write_data (Address_00000000001, Data_write_11100111)
   call Write_data (Address_00000000011, Data_write_11000011)
   call Write_data (Address_00000000111, Data_write_10000001)
   call Write_data (Address_00000001111, Data_write_00000000)
   call Write_data (Address_00000011111, Data_write_00010001)
   call Write_data (Address_00000111111, Data_write_00110011)
   call Write_data (Address_00001111111, Data_write_01110111)
   call Write_data (Address_00011111111, Data_write_01011010)
   call Write_data (Address_00111111111, Data_write_11011011)
   call Write_data (Address_01111111111, Data_write_10011001)
   call Write_data (Address_11111111111, Data_write_10100101)

   call Read_data (Address_00000000000, Data_read_11111111)
   call Read_data (Address_00000000001, Data_read_11100111)
   call Read_data (Address_00000000011, Data_read_11000011)
   call Read_data (Address_00000000111, Data_read_10000001)
   call Read_data (Address_00000001111, Data_read_00000000)
   call Read_data (Address_00000011111, Data_read_00010001)
   call Read_data (Address_00000111111, Data_read_00110011)
   call Read_data (Address_00001111111, Data_read_01110111)
   call Read_data (Address_00011111111, Data_read_01011010)
   call Read_data (Address_00111111111, Data_read_11011011)
   call Read_data (Address_01111111111, Data_read_10011001)
   call Read_data (Address_11111111111, Data_read_10100101)
end unit

unit "Chip_select SA0"
   execute  Disable
   call Write_data (Address_00000000000, Data_write_00000000)
   execute  Address_00000000000
   execute  Write_enable_CS_false
   execute  Data_write_10101010_CS_false
   execute  Disable
   call Read_data (Address_00000000000, Data_read_00000000)
end unit

! To test output enable, the tri-state outputs must be pulled up.

unit "Output enable test"
      execute  Disable
      call Write_data (Address_00000000000, Data_write_00000000) !If pulled up
      execute  Output_enable_false
      execute  Address_00000000000
      execute  Data_read_11111111    ! If pulled up
end unit



!    End of test