!!!!    6    0    1  986760460  Va063                                         

! Device           : 4801
! Function         : Static RAM 3-state 1k x 8
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

!warning "Pull-ups are required to test high-impedance outputs."

!         VSS            to pin    12   GND

assign    VCC            to pins   24
assign    GND            to pins   12

assign    Address        to pins   22,23,1,2,3,4,5,6,7,8

assign    Data           to pins   17,16,15,14,13,11,10,9
assign    Data_D0        to pins   9    !AT Added for minimum pin test.
assign    Data_D1        to pins   10   !AT Added for minimum pin test.
assign    Data_D2        to pins   11   !AT Added for minimum pin test.
assign    Data_D3        to pins   13   !AT Added for minimum pin test.
assign    Data_D4        to pins   14   !AT Added for minimum pin test.
assign    Data_D5        to pins   15   !AT Added for minimum pin test.
assign    Data_D6        to pins   16   !AT Added for minimum pin test.
assign    Data_D7        to pins   17   !AT Added for minimum pin test.

assign    Chip_enable_bar       to pins   18
assign    Write_enable_bar      to pins   21
assign    Output_enable_bar     to pins   20
assign    No_Connection         to pins   19    ! Unused pin

family    TTL

power     VCC, GND

inputs    Address, Write_enable_bar, Chip_enable_bar
inputs    Output_enable_bar

bidirectional  Data
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.
bidirectional  Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test.

nondigital No_connection

when  Output_enable_bar    is    "1"   inactive Data
when  Chip_enable_bar      is    "1"   inactive Data
when  Write_enable_bar     is    "1"   inputs   Data
when  Write_enable_bar     is    "0"   outputs  Data

trace  Data  to  Address, Write_enable_bar, Chip_enable_bar
trace  Data  to  Output_enable_bar

disable   Data   with  Write_enable_bar    to   "0"
disable   Data   with  Output_enable_bar   to   "1"
disable   Data   with  Chip_enable_bar     to   "1"

!***************************************************************
!***************************************************************

vector    Disable
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "1"
end vector

vector    Chip_enable_true
     set  Address             to   "kkkkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "0"
     set  Output_enable_bar   to   "k"
end vector

vector    Write_enable
     set  Address             to   "kkkkkkkkkk"
     set  Write_enable_bar    to   "0"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "k"
end vector

vector    Write_enable_true
     set  Address             to   "kkkkkkkkkk"
     set  Write_enable_bar    to   "0"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "0"
end vector

vector    Write_enable_false
     drive  Data
     set  Data                to   "kkkkkkkk"
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "k"
end vector

vector    Chip_enable_false
     drive  Data
     set  Data                to   "kkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "k"
end vector

vector    Read_enable
     set  Address             to   "kkkkkkkkkk"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "0"
     set  Output_enable_bar   to   "0"
end vector

vector    Read_disable
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "1"
end vector

vector    Address_0000000000
     initialize to  Disable
     set  Address   to   "0000000000"
end vector

vector    Address_0000000001
     initialize to  Disable
     set  Address   to   "0000000001"
end vector

vector    Address_0000000011
     initialize to  Disable
     set  Address   to   "0000000011"
end vector

vector    Address_0000000111
     initialize to  Disable
     set  Address   to   "0000000111"
end vector

vector    Address_0000001111
     initialize to  Disable
     set  Address   to   "0000001111"
end vector

vector    Address_0000011111
     initialize to  Disable
     set  Address   to   "0000011111"
end vector

vector    Address_0000111111
     initialize to  Disable
     set  Address   to   "0000111111"
end vector

vector    Address_0001111111
     initialize to  Disable
     set  Address   to   "0001111111"
end vector

vector    Address_0011111111
     initialize to  Disable
     set  Address   to   "0011111111"
end vector

vector    Address_0111111111
     initialize to  Disable
     set  Address   to   "0111111111"
end vector

vector    Address_1111111111
     initialize to  Disable
     set  Address   to   "1111111111"
end vector

vector    Data_write_00000000
     initialize to  Write_enable
     drive  Data
     set Data       to   "00000000"
end vector

vector    Data_write_00000001
     initialize to  Write_enable
     drive  Data
     set Data       to   "00000001"
end vector

vector    Data_write_00000011
     initialize to  Write_enable
     drive  Data
     set Data       to   "00000011"
end vector

vector    Data_write_00000111
     initialize to  Write_enable
     drive  Data
     set Data       to   "00000111"
end vector

vector    Data_write_00001111
     initialize to  Write_enable
     drive  Data
     set Data       to   "00001111"
end vector

vector    Data_write_00011111
     initialize to  Write_enable
     drive  Data
     set Data       to   "00011111"
end vector

vector    Data_write_00111111
     initialize to  Write_enable
     drive  Data
     set Data       to   "00111111"
end vector

vector    Data_write_01111111
     initialize to  Write_enable
     drive  Data
     set Data       to   "01111111"
end vector

vector    Data_write_11111111
     initialize to  Write_enable
     drive  Data
     set Data       to   "11111111"
end vector

vector    Data_write_10101010
     initialize to  Write_enable
     drive  Data
     set Data       to   "10101010"
end vector

vector    Data_write_01010101
     initialize to  Write_enable
     drive  Data
     set Data       to   "01010101"
end vector

vector    Data_write_11111111_CE_false
     drive  Data
     set Address           to  "kkkkkkkkkk"
     set Write_enable_bar  to  "0"
     set Chip_enable_bar   to  "k"
     set Output_enable_bar to  "0"
     set Data              to  "11111111"
end vector

vector    Data_read_00000000
     initialize to  Read_enable
     receive  Data
     set Data       to   "00000000"
end vector

vector    Data_read_00000001
     initialize to  Read_enable
     receive  Data
     set Data       to   "00000001"
end vector

vector    Data_read_00000011
     initialize to  Read_enable
     receive  Data
     set Data       to   "00000011"
end vector

vector    Data_read_00000111
     initialize to  Read_enable
     receive  Data
     set Data       to   "00000111"
end vector

vector    Data_read_00001111
     initialize to  Read_enable
     receive  Data
     set Data       to   "00001111"
end vector

vector    Data_read_00011111
     initialize to  Read_enable
     receive  Data
     set Data       to   "00011111"
end vector

vector    Data_read_00111111
     initialize to  Read_enable
     receive  Data
     set Data       to   "00111111"
end vector

vector    Data_read_01111111
     initialize to  Read_enable
     receive  Data
     set Data       to   "01111111"
end vector

vector    Data_read_11111111
     initialize to  Read_enable
     receive  Data
     set Data       to   "11111111"
end vector

vector    Data_read_10101010
     initialize to  Read_enable
     receive  Data
     set Data       to   "10101010"
end vector

vector    Data_read_01010101
     initialize to  Read_enable
     receive  Data
     set Data       to   "01010101"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    WEb_hi_D0
     drive  Data_D0
     set  Data_D0             to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "k"
end vector

vector    WEb_hi_D1
     drive  Data_D1
     set  Data_D1             to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "k"
end vector

vector    WEb_hi_D2
     drive  Data_D2
     set  Data_D2             to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "k"
end vector

vector    WEb_hi_D3
     drive  Data_D3
     set  Data_D3             to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "k"
end vector

vector    WEb_hi_D4
     drive  Data_D4
     set  Data_D4             to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "k"
end vector

vector    WEb_hi_D5
     drive  Data_D5
     set  Data_D5             to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "k"
end vector

vector    WEb_hi_D6
     drive  Data_D6
     set  Data_D6             to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "k"
end vector

vector    WEb_hi_D7
     drive  Data_D7
     set  Data_D7             to   "k"
     set  Write_enable_bar    to   "1"
     set  Chip_enable_bar     to   "k"
     set  Output_enable_bar   to   "k"
end vector

vector    CEb_hi_D0
     drive  Data_D0
     set  Data_D0             to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "k"
end vector

vector    CEb_hi_D1
     drive  Data_D1
     set  Data_D1             to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "k"
end vector

vector    CEb_hi_D2
     drive  Data_D2
     set  Data_D2             to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "k"
end vector

vector    CEb_hi_D3
     drive  Data_D3
     set  Data_D3             to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "k"
end vector

vector    CEb_hi_D4
     drive  Data_D4
     set  Data_D4             to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "k"
end vector

vector    CEb_hi_D5
     drive  Data_D5
     set  Data_D5             to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "k"
end vector

vector    CEb_hi_D6
     drive  Data_D6
     set  Data_D6             to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "k"
end vector

vector    CEb_hi_D7
     drive  Data_D7
     set  Data_D7             to   "k"
     set  Write_enable_bar    to   "k"
     set  Chip_enable_bar     to   "1"
     set  Output_enable_bar   to   "k"
end vector

vector    Data_write_D0_0
     initialize to  WEb_hi_D0
     drive  Data_D0
     set Data_D0    to   "0"
end vector

vector    Data_write_D0_1
     initialize to  WEb_hi_D0
     drive  Data_D0
     set Data_D0    to   "1"
end vector

vector    Data_write_D1_0
     initialize to  WEb_hi_D1
     drive  Data_D1
     set Data_D1    to   "0"
end vector

vector    Data_write_D1_1
     initialize to  WEb_hi_D1
     drive  Data_D1
     set Data_D1    to   "1"
end vector

vector    Data_write_D2_0
     initialize to  WEb_hi_D2
     drive  Data_D2
     set Data_D2    to   "0"
end vector

vector    Data_write_D2_1
     initialize to  WEb_hi_D2
     drive  Data_D2
     set Data_D2    to   "1"
end vector

vector    Data_write_D3_0
     initialize to  WEb_hi_D3
     drive  Data_D3
     set Data_D3    to   "0"
end vector

vector    Data_write_D3_1
     initialize to  WEb_hi_D3
     drive  Data_D3
     set Data_D3    to   "1"
end vector

vector    Data_write_D4_0
     initialize to  WEb_hi_D4
     drive  Data_D4
     set Data_D4    to   "0"
end vector

vector    Data_write_D4_1
     initialize to  WEb_hi_D4
     drive  Data_D4
     set Data_D4    to   "1"
end vector

vector    Data_write_D5_0
     initialize to  WEb_hi_D5
     drive  Data_D5
     set Data_D5    to   "0"
end vector

vector    Data_write_D5_1
     initialize to  WEb_hi_D5
     drive  Data_D5
     set Data_D5    to   "1"
end vector

vector    Data_write_D6_0
     initialize to  WEb_hi_D6
     drive  Data_D6
     set Data_D6    to   "0"
end vector

vector    Data_write_D6_1
     initialize to  WEb_hi_D6
     drive  Data_D6
     set Data_D6    to   "1"
end vector

vector    Data_write_D7_0
     initialize to  WEb_hi_D7
     drive  Data_D7
     set Data_D7    to   "0"
end vector

vector    Data_write_D7_1
     initialize to  WEb_hi_D7
     drive  Data_D7
     set Data_D7    to   "1"
end vector

vector    Data_read_D0_0
     initialize to  Read_enable
     receive  Data_D0
     set Data_D0    to   "0"
end vector

vector    Data_read_D0_1
     initialize to  Read_enable
     receive  Data_D0
     set Data_D0    to   "1"
end vector

vector    Data_read_D1_0
     initialize to  Read_enable
     receive  Data_D1
     set Data_D1    to   "0"
end vector

vector    Data_read_D1_1
     initialize to  Read_enable
     receive  Data_D1
     set Data_D1    to   "1"
end vector

vector    Data_read_D2_0
     initialize to  Read_enable
     receive  Data_D2
     set Data_D2    to   "0"
end vector

vector    Data_read_D2_1
     initialize to  Read_enable
     receive  Data_D2
     set Data_D2    to   "1"
end vector

vector    Data_read_D3_0
     initialize to  Read_enable
     receive  Data_D3
     set Data_D3    to   "0"
end vector

vector    Data_read_D3_1
     initialize to  Read_enable
     receive  Data_D3
     set Data_D3    to   "1"
end vector

vector    Data_read_D4_0
     initialize to  Read_enable
     receive  Data_D4
     set Data_D4    to   "0"
end vector

vector    Data_read_D4_1
     initialize to  Read_enable
     receive  Data_D4
     set Data_D4    to   "1"
end vector

vector    Data_read_D5_0
     initialize to  Read_enable
     receive  Data_D5
     set Data_D5    to   "0"
end vector

vector    Data_read_D5_1
     initialize to  Read_enable
     receive  Data_D5
     set Data_D5    to   "1"
end vector

vector    Data_read_D6_0
     initialize to  Read_enable
     receive  Data_D6
     set Data_D6    to   "0"
end vector

vector    Data_read_D6_1
     initialize to  Read_enable
     receive  Data_D6
     set Data_D6    to   "1"
end vector

vector    Data_read_D7_0
     initialize to  Read_enable
     receive  Data_D7
     set Data_D7    to   "0"
end vector

vector    Data_read_D7_1
     initialize to  Read_enable
     receive  Data_D7
     set Data_D7    to   "1"
end vector

!***************************************************************
!***************************************************************

sub  Write_data (Address, Data)
     execute   Address
     execute   Chip_enable_true
     execute   Data
     execute   Chip_enable_false
     execute   Write_enable_false
end sub

sub  Read_data (Address, Data)
     execute   Address
     execute   Data
     execute   Read_disable
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, CEb_hi_Dx, WEb_hi_Dx)
     execute   Address
     execute   Chip_enable_true
     execute   Data_Dx
     execute   CEb_hi_Dx
     execute   WEb_hi_Dx
end sub

!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

  call Write_data_Dx (Address_0000000000, Data_write_D0_0, CEb_hi_D0, WEb_hi_D0)
  call Read_data (Address_0000000000, Data_read_D0_0)

  call Write_data_Dx (Address_0000000000, Data_write_D0_1, CEb_hi_D0, WEb_hi_D0)
  call Read_data (Address_0000000000, Data_read_D0_1)

end unit

unit   "awaretest D1 Test"

  call Write_data_Dx (Address_0000000000, Data_write_D1_0, CEb_hi_D1, WEb_hi_D1)
  call Read_data (Address_0000000000, Data_read_D1_0)

  call Write_data_Dx (Address_0000000000, Data_write_D1_1, CEb_hi_D1, WEb_hi_D1)
  call Read_data (Address_0000000000, Data_read_D1_1)

end unit

unit   "awaretest D2 Test"

  call Write_data_Dx (Address_0000000000, Data_write_D2_0, CEb_hi_D2, WEb_hi_D2)
  call Read_data (Address_0000000000, Data_read_D2_0)

  call Write_data_Dx (Address_0000000000, Data_write_D2_1, CEb_hi_D2, WEb_hi_D2)
  call Read_data (Address_0000000000, Data_read_D2_1)

end unit

unit   "awaretest D3 Test"

  call Write_data_Dx (Address_0000000000, Data_write_D3_0, CEb_hi_D3, WEb_hi_D3)
  call Read_data (Address_0000000000, Data_read_D3_0)

  call Write_data_Dx (Address_0000000000, Data_write_D3_1, CEb_hi_D3, WEb_hi_D3)
  call Read_data (Address_0000000000, Data_read_D3_1)

end unit

unit   "awaretest D4 Test"

  call Write_data_Dx (Address_0000000000, Data_write_D4_0, CEb_hi_D4, WEb_hi_D4)
  call Read_data (Address_0000000000, Data_read_D4_0)

  call Write_data_Dx (Address_0000000000, Data_write_D4_1, CEb_hi_D4, WEb_hi_D4)
  call Read_data (Address_0000000000, Data_read_D4_1)

end unit

unit   "awaretest D5 Test"

  call Write_data_Dx (Address_0000000000, Data_write_D5_0, CEb_hi_D5, WEb_hi_D5)
  call Read_data (Address_0000000000, Data_read_D5_0)

  call Write_data_Dx (Address_0000000000, Data_write_D5_1, CEb_hi_D5, WEb_hi_D5)
  call Read_data (Address_0000000000, Data_read_D5_1)

end unit

unit   "awaretest D6 Test"

  call Write_data_Dx (Address_0000000000, Data_write_D6_0, CEb_hi_D6, WEb_hi_D6)
  call Read_data (Address_0000000000, Data_read_D6_0)

  call Write_data_Dx (Address_0000000000, Data_write_D6_1, CEb_hi_D6, WEb_hi_D6)
  call Read_data (Address_0000000000, Data_read_D6_1)

end unit

unit   "awaretest D7 Test"

  call Write_data_Dx (Address_0000000000, Data_write_D7_0, CEb_hi_D7, WEb_hi_D7)
  call Read_data (Address_0000000000, Data_read_D7_0)

  call Write_data_Dx (Address_0000000000, Data_write_D7_1, CEb_hi_D7, WEb_hi_D7)
  call Read_data (Address_0000000000, Data_read_D7_1)

end unit

unit "Test RAM"
     call Write_data (Address_0000000000, Data_write_00000000)
     call Write_data (Address_0000000001, Data_write_00000001)
     call Write_data (Address_0000000011, Data_write_00000011)
     call Write_data (Address_0000000111, Data_write_00000111)
     call Write_data (Address_0000001111, Data_write_00001111)
     call Write_data (Address_0000011111, Data_write_00011111)
     call Write_data (Address_0000111111, Data_write_00111111)
     call Write_data (Address_0001111111, Data_write_01111111)
     call Write_data (Address_0011111111, Data_write_11111111)
     call Write_data (Address_0111111111, Data_write_10101010)
     call Write_data (Address_1111111111, Data_write_01010101)
     call Read_data (Address_0000000000, Data_read_00000000)
     call Read_data (Address_0000000001, Data_read_00000001)
     call Read_data (Address_0000000011, Data_read_00000011)
     call Read_data (Address_0000000111, Data_read_00000111)
     call Read_data (Address_0000001111, Data_read_00001111)
     call Read_data (Address_0000011111, Data_read_00011111)
     call Read_data (Address_0000111111, Data_read_00111111)
     call Read_data (Address_0001111111, Data_read_01111111)
     call Read_data (Address_0011111111, Data_read_11111111)
     call Read_data (Address_0111111111, Data_read_10101010)
     call Read_data (Address_1111111111, Data_read_01010101)
end unit



unit "Test  Chip_enable"
     call Write_data (Address_0000000000, Data_write_00000000)
     execute   Address_0000000000
     execute   Chip_enable_false
     execute   Data_write_11111111_CE_false
     execute   Write_enable_false
     call Read_data (Address_0000000000, Data_read_00000000)
end unit

!    End of test