!!!!    6    0    1  987109319  V5b2a                                         

! Device           : 4416
! Function         : Ram_dynamic  3_state   16k x 4
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

!Note: This device has outputs that can be put in the high impedance state.
!      Inorder to test the Output_enable (pin 1) pullup resistors will be
!      needed, and the last unit must be uncommented.

vector cycle  1u
receive delay 900n

assign       VCC                 to pins          9
assign       GND                 to pins          18

assign       Output_enable       to pins          1
assign       Data                to pins          17,15,3,2
assign       Data_D0             to pins   2    !AT Added for minimum pin test.
assign       Data_D1             to pins   3    !AT Added for minimum pin test.
assign       Data_D2             to pins   15   !AT Added for minimum pin test.
assign       Data_D3             to pins   17   !AT Added for minimum pin test.
assign       Write_bar           to pins          4
assign       RAS_bar             to pins          5
assign       CAS_bar             to pins          16
assign       Address_bus         to pins          10,6,7,8,11,12
assign       Address_bus         to pins          13,14

family       TTL

power        VCC, GND

inputs       Output_enable, Write_bar, RAS_bar, CAS_bar, Address_bus

bidirectional  Data
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.

set load on groups Data      to pull up

when     Output_enable  is    "1"   inactive    Data
when     Write_bar      is    "0"   inputs   Data
when     Write_bar      is    "1"   outputs  Data
when     CAS_bar        is    "1"   inactive Data

trace  Data to Output_enable, Write_bar, RAS_bar, CAS_bar, Address_bus

disable      Data        with         Output_enable to       "1"


!*****************************************************************************
!*****************************************************************************
 vector Reset
    set     RAS_bar             to          "1"
    set     CAS_bar             to          "1"
    set     Write_bar           to          "0"
    set     Output_enable       to          "0"
    set     Address_bus         to          "00000000"
end vector

 vector Keep_Control
    set     RAS_bar             to          "k"
    set     CAS_bar             to          "k"
    set     Write_bar           to          "k"
    set     Output_enable       to          "k"
    set     Address_bus         to          "kkkkkkkk"
end vector

vector       Write_RAS_bar_low
    initialize to Keep_Control
    drive Data
    set     Data                to          "kkkk"
    set     RAS_bar             to          "0"
end vector

vector       Write_CAS_bar_low
    initialize to Keep_Control
    drive Data
    set     Data                to          "kkkk"
    set     CAS_bar             to          "0"
end vector

vector       RAS_bar_low
    initialize to Keep_Control
    set     RAS_bar             to          "0"
end vector

vector       CAS_bar_low
    initialize to Keep_Control
    set     CAS_bar             to          "0"
end vector

vector       Read_true
    initialize to Keep_Control
    set     Output_enable       to          "0"
    set     Write_bar           to          "1"
end vector

vector       Write_true
    initialize to Keep_Control
    set     Output_enable       to          "1"
    set     Write_bar           to          "0"
end vector

vector       RASCAS_high
    initialize to Keep_Control
    set     RAS_bar             to          "1"
    set     CAS_bar             to          "1"
end vector

vector       Disable
    initialize to Keep_Control
    set     Output_enable       to          "1"
end vector

vector       Read_Data_5
    initialize to Read_true
    receive Data
    set     Data                to          "0101"
    set     Output_enable       to          "0"
end vector

vector       Read_Data_A
    initialize to Read_true
    receive Data
    set     Data                to          "1010"
    set     Output_enable       to          "0"
end vector

vector       Disable_test
    initialize to Read_true
    receive Data
    set     Data                to          "1111"
    set     Output_enable       to          "1"
end vector

vector       Address_00000000
    initialize to Keep_Control

    set     Address_bus         to          "00000000"
end vector

vector       Address_00000001
    initialize to Keep_Control
    set     Address_bus         to          "00000001"
end vector

vector       Address_00000011
    initialize to Keep_Control
    set     Address_bus         to          "00000011"
end vector

vector       Address_00000111
    initialize to Keep_Control
    set     Address_bus         to          "00000111"
end vector

vector      Address_00001111
    initialize to Keep_Control
    set     Address_bus         to          "00001111"
end vector

vector       Address_00011111
    initialize to Keep_Control
    set     Address_bus         to          "00011111"
end vector

vector       Address_00111111
    initialize to Keep_Control
    set     Address_bus         to          "00111111"
end vector

vector       Address_01111111
    initialize to Keep_Control
    set     Address_bus         to          "01111111"
end vector

vector       Address_11111111
    initialize to Keep_Control
    set     Address_bus         to          "11111111"
end vector

vector       Data_In_5
    initialize to Keep_Control
    drive Data
    set     Address_bus         to           "kkkkkkkk"
    set     Data                to           "0101"
    set     Output_enable       to           "1"
end vector

vector       Data_In_A
    initialize to Keep_Control
    drive Data
    set     Address_bus         to           "kkkkkkkk"
    set     Data                to           "1010"
    set     Output_enable       to           "1"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector       W_RASb_low_D0
    initialize to Keep_Control
    drive Data_D0
    set     Data_D0             to          "k"
    set     RAS_bar             to          "0"
end vector

vector       W_CASb_low_D0
    initialize to Keep_Control
    drive Data_D0
    set     Data_D0             to          "k"
    set     CAS_bar             to          "0"
end vector

vector       Read_Data_D0_0
    initialize to Read_true
    receive Data_D0
    set     Data_D0             to          "0"
    set     Output_enable       to          "0"
end vector

vector       Read_Data_D0_1
    initialize to Read_true
    receive Data_D0
    set     Data_D0             to          "1"
    set     Output_enable       to          "0"
end vector

vector       Data_In_D0_0
    initialize to Keep_Control
    drive Data_D0
    set     Address_bus         to           "kkkkkkkk"
    set     Data_D0             to           "0"
    set     Output_enable       to           "1"
end vector

vector       Data_In_D0_1
    initialize to Keep_Control
    drive Data_D0
    set     Address_bus         to           "kkkkkkkk"
    set     Data_D0             to           "1"
    set     Output_enable       to           "1"
end vector

vector       W_RASb_low_D1
    initialize to Keep_Control
    drive Data_D1
    set     Data_D1             to          "k"
    set     RAS_bar             to          "0"
end vector

vector       W_CASb_low_D1
    initialize to Keep_Control
    drive Data_D1
    set     Data_D1             to          "k"
    set     CAS_bar             to          "0"
end vector

vector       Read_Data_D1_0
    initialize to Read_true
    receive Data_D1
    set     Data_D1             to          "0"
    set     Output_enable       to          "0"
end vector

vector       Read_Data_D1_1
    initialize to Read_true
    receive Data_D1
    set     Data_D1             to          "1"
    set     Output_enable       to          "0"
end vector

vector       Data_In_D1_0
    initialize to Keep_Control
    drive Data_D1
    set     Address_bus         to           "kkkkkkkk"
    set     Data_D1             to           "0"
    set     Output_enable       to           "1"
end vector

vector       Data_In_D1_1
    initialize to Keep_Control
    drive Data_D1
    set     Address_bus         to           "kkkkkkkk"
    set     Data_D1             to           "1"
    set     Output_enable       to           "1"
end vector

vector       W_RASb_low_D2
    initialize to Keep_Control
    drive Data_D2
    set     Data_D2             to          "k"
    set     RAS_bar             to          "0"
end vector

vector       W_CASb_low_D2
    initialize to Keep_Control
    drive Data_D2
    set     Data_D2             to          "k"
    set     CAS_bar             to          "0"
end vector

vector       Read_Data_D2_0
    initialize to Read_true
    receive Data_D2
    set     Data_D2             to          "0"
    set     Output_enable       to          "0"
end vector

vector       Read_Data_D2_1
    initialize to Read_true
    receive Data_D2
    set     Data_D2             to          "1"
    set     Output_enable       to          "0"
end vector

vector       Data_In_D2_0
    initialize to Keep_Control
    drive Data_D2
    set     Address_bus         to           "kkkkkkkk"
    set     Data_D2             to           "0"
    set     Output_enable       to           "1"
end vector

vector       Data_In_D2_1
    initialize to Keep_Control
    drive Data_D2
    set     Address_bus         to           "kkkkkkkk"
    set     Data_D2             to           "1"
    set     Output_enable       to           "1"
end vector

vector       W_RASb_low_D3
    initialize to Keep_Control
    drive Data_D3
    set     Data_D3             to          "k"
    set     RAS_bar             to          "0"
end vector

vector       W_CASb_low_D3
    initialize to Keep_Control
    drive Data_D3
    set     Data_D3             to          "k"
    set     CAS_bar             to          "0"
end vector

vector       Read_Data_D3_0
    initialize to Read_true
    receive Data_D3
    set     Data_D3             to          "0"
    set     Output_enable       to          "0"
end vector

vector       Read_Data_D3_1
    initialize to Read_true
    receive Data_D3
    set     Data_D3             to          "1"
    set     Output_enable       to          "0"
end vector

vector       Data_In_D3_0
    initialize to Keep_Control
    drive Data_D3
    set     Address_bus         to           "kkkkkkkk"
    set     Data_D3             to           "0"
    set     Output_enable       to           "1"
end vector

vector       Data_In_D3_1
    initialize to Keep_Control
    drive Data_D3
    set     Address_bus         to           "kkkkkkkk"
    set     Data_D3             to           "1"
    set     Output_enable       to           "1"
end vector

!*****************************************************************************
!*****************************************************************************

!       Initialize performs 10 RAS only refresh cycles necessary for proper
!       chip operation after turn-on
!       Ram_Test tests with a walking 5 pattern on the data pins and a
!       graycode pattern on the address bus.  At all times ROW Address
!       is equal to COLUMN Address, therefore once an address has been
!       set, 'keeps' are used to hold the address while RAS_bar and
!       CAS_bar latch the address into row/col information.
!       Testing in this manner checks for all pin faults in an all pins
!       free topology.



sub          Initialize
    repeat 10 times
            execute             RAS_bar_low
            execute             RASCAS_high
    end repeat
end sub


sub          Write_Data (Address,Data)
            execute             Write_true
            execute             Data
            execute             Address
            execute             Write_RAS_bar_low
            execute             Write_CAS_bar_low
            execute             RASCAS_high
end sub

sub          Read_Data (Address,Data)
            execute             Read_true
            execute             Address
            execute             RAS_bar_low
            execute             CAS_bar_low
            execute             Data
            execute             RASCAS_high
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_Data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_Data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (data). This reference can be modified in the
!AT call statement.

sub  Write_Data_Dx (Address, Data_Dx, W_RASb_low_Dx, W_CASb_low_Dx)
            execute             Write_true
            execute             Data_Dx
            execute             Address
            execute             W_RASb_low_Dx
            execute             W_CASb_low_Dx
            execute             RASCAS_high
end sub

!*****************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

  execute Reset
  call  Initialize

  call Write_Data_Dx (Address_00000000,Data_In_D0_0,W_RASb_low_D0,W_CASb_low_D0)
  call Read_Data (Address_00000000,Read_Data_D0_0)

  call Write_Data_Dx (Address_00000000,Data_In_D0_1,W_RASb_low_D0,W_CASb_low_D0)
  call Read_Data (Address_00000000,Read_Data_D0_1)

end unit

unit   "awaretest D1 Test"

  execute Reset
  call  Initialize

  call Write_Data_Dx (Address_00000000,Data_In_D1_0,W_RASb_low_D1,W_CASb_low_D1)
  call Read_Data (Address_00000000,Read_Data_D1_0)

  call Write_Data_Dx (Address_00000000,Data_In_D1_1,W_RASb_low_D1,W_CASb_low_D1)
  call Read_Data (Address_00000000,Read_Data_D1_1)

end unit

unit   "awaretest D2 Test"

  execute Reset
  call  Initialize

  call Write_Data_Dx (Address_00000000,Data_In_D2_0,W_RASb_low_D2,W_CASb_low_D2)
  call Read_Data (Address_00000000,Read_Data_D2_0)

  call Write_Data_Dx (Address_00000000,Data_In_D2_1,W_RASb_low_D2,W_CASb_low_D2)
  call Read_Data (Address_00000000,Read_Data_D2_1)

end unit

unit   "awaretest D3 Test"

  execute Reset
  call  Initialize

  call Write_Data_Dx (Address_00000000,Data_In_D3_0,W_RASb_low_D3,W_CASb_low_D3)
  call Read_Data (Address_00000000,Read_Data_D3_0)

  call Write_Data_Dx (Address_00000000,Data_In_D3_1,W_RASb_low_D3,W_CASb_low_D3)
  call Read_Data (Address_00000000,Read_Data_D3_1)

end unit

unit         "Initialize_Ram"
            execute Reset
            call         Initialize
            call         Write_Data (Address_00000000,Data_In_5)
            call         Write_Data (Address_00000001,Data_In_5)
            call         Write_Data (Address_00000011,Data_In_5)
            call         Write_Data (Address_00000111,Data_In_5)
            call         Write_Data (Address_00001111,Data_In_5)
            call         Write_Data (Address_00011111,Data_In_5)
            call         Write_Data (Address_00111111,Data_In_5)
            call         Write_Data (Address_01111111,Data_In_5)
            call         Write_Data (Address_11111111,Data_In_5)
end unit

unit         "Ram_Test"
            execute Reset
            call         Read_Data (Address_00000000,Read_Data_5)
            call         Write_Data (Address_00000000,Data_In_A)
            call         Read_Data (Address_00000000,Read_Data_A)

            call         Read_Data (Address_00000001,Read_Data_5)
            call         Write_Data (Address_00000001,Data_In_A)
            call         Read_Data (Address_00000001,Read_Data_A)

            call         Read_Data (Address_00000011,Read_Data_5)
            call         Write_Data (Address_00000011,Data_In_A)
            call         Read_Data (Address_00000011,Read_Data_A)

            call         Read_Data (Address_00000111,Read_Data_5)
            call         Write_Data (Address_00000111,Data_In_A)
            call         Read_Data (Address_00000111,Read_Data_A)

            call         Read_Data (Address_00001111,Read_Data_5)
            call         Write_Data (Address_00001111,Data_In_A)
            call         Read_Data (Address_00001111,Read_Data_A)

            call         Read_Data (Address_00011111,Read_Data_5)
            call         Write_Data (Address_00011111,Data_In_A)
            call         Read_Data (Address_00011111,Read_Data_A)

            call         Read_Data (Address_00111111,Read_Data_5)
            call         Write_Data (Address_00111111,Data_In_A)
            call         Read_Data (Address_00111111,Read_Data_A)

            call         Read_Data (Address_01111111,Read_Data_5)
            call         Write_Data (Address_01111111,Data_In_A)
            call         Read_Data (Address_01111111,Read_Data_A)

            call         Read_Data (Address_11111111,Read_Data_5)
            call         Write_Data (Address_11111111,Data_In_A)
            call         Read_Data (Address_11111111,Read_Data_A)
end unit

unit  "Enable test"
            execute Reset
            call         Read_Data (Address_11111111,Read_Data_A)
            execute RAS_bar_low
            execute CAS_bar_low
            execute Disable
            execute Disable_test
end unit

!       End of test