!!!!    6    0    1  987013184  V4524                                         

! Device           : 2210
! Function         : 256 Bit Nonvolatile Static RAM
! revision         : B.01.00
! safeguard        : standard_ttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

   warning "*******************************************************"
   warning "The unit Test Nonvolatile Memory requires approximately"
   warning "20ms due to the required storage time of 10ms for the"
   warning "nonvolatile memory.  The unit should be commented out"
   warning "if a shorter test is desired."
   warning "*******************************************************"
   warning "The vector Tristate must be modified to tristate all"
   warning "Disablegroup drivers if the unit Test Nonvolatile"
   warning "Memory is not commented.  Use safeguard cool while"
   warning "executing the test."
   warning "*******************************************************"

vector cycle   500n
receive delay  400n

assign   VCC               to pins  18
assign   GND               to pins   8

assign   A5_A0             to pins  16,  2,  3,  4,  5,  6
assign   IO4_IO1           to pins  15, 14, 13, 12
assign   IO1               to pins  12 !AT Added for minimum pin test.
assign   IO2               to pins  13 !AT Added for minimum pin test.
assign   IO3               to pins  14 !AT Added for minimum pin test.
assign   IO4               to pins  15 !AT Added for minimum pin test.

assign   CS_bar            to pins   7
assign   WE_bar            to pins  11

assign   Store_bar         to pins   9
assign   Array_Recall_bar  to pins  10

assign   NC                to pins   1, 17

family   TTL

power    VCC, GND

inputs   A5_A0
inputs   CS_bar, Store_bar, WE_bar, Array_Recall_bar

bidirectional  IO4_IO1
bidirectional  IO1, IO2, IO3, IO4            !AT Added for min. pin test.

nondigital  NC

disable  IO4_IO1  with  CS_bar  to "1"
disable  IO4_IO1  with  WE_bar  to "0"

when  CS_bar   is "1"   inactive IO4_IO1
when  WE_bar   is "0"   inactive IO4_IO1

! Note: default trace specification is used

!
!*******************************************************************************
!

vector   Initialize
   drive IO4_IO1
   set   IO4_IO1  to "0000"
   set   A5_A0    to "000000"
   set   CS_bar   to "0"
   set   WE_bar   to "1"
   set   Store_bar         to "1"
   set   Array_Recall_bar  to "1"
end vector

vector   Keep_Control
   drive IO4_IO1
   set   IO4_IO1  to "kkkk"
   set   A5_A0    to "kkkkkk"
   set   CS_bar   to "k"
   set   WE_bar   to "k"
   set   Store_bar         to "k"
   set   Array_Recall_bar  to "k"
end vector

vector   End_Cycle
   drive IO4_IO1
   set   IO4_IO1  to "kkkk"
   set   A5_A0    to "kkkkkk"
   set   CS_bar   to "k"
   set   WE_bar   to "0"
   set   Store_bar         to "k"
   set   Array_Recall_bar  to "k"
end vector

vector   Add_000000
   initialize to Keep_Control
   set   WE_bar   to "1"
   set   A5_A0    to "000000"
end vector

vector   Add_000001
   initialize to Keep_Control
   set   WE_bar   to "1"
   set   A5_A0    to "000001"
end vector

vector   Add_000010
   initialize to Keep_Control
   set   WE_bar   to "1"
   set   A5_A0    to "000010"
end vector

vector   Add_000100
   initialize to Keep_Control
   set   WE_bar   to "1"
   set   A5_A0    to "000100"
end vector

vector   Add_001000
   initialize to Keep_Control
   set   WE_bar   to "1"
   set   A5_A0    to "001000"
end vector

vector   Add_010000
   initialize to Keep_Control
   set   WE_bar   to "1"
   set   A5_A0    to "010000"
end vector

vector   Add_100000
   initialize to Keep_Control
   set   WE_bar   to "1"
   set   A5_A0    to "100000"
end vector

vector   Add_111111
   initialize to Keep_Control
   set   WE_bar   to "1"
   set   A5_A0    to "111111"
end vector

vector   Data_0101D
   initialize to Keep_Control
   set   IO4_IO1  to "0101"
end vector

vector   Data_1010D
   initialize to Keep_Control
   set   IO4_IO1  to "1010"
end vector

vector   Data_0101R
   initialize to Keep_Control
   receive  IO4_IO1
   set   IO4_IO1  to "0101"
end vector

vector   Data_1010R
   initialize to Keep_Control
   receive  IO4_IO1
   set   IO4_IO1  to "1010"
end vector

vector   CS_true
   initialize to Keep_Control
   set   WE_bar      to "1"
   set   CS_bar      to "0"
end vector

vector   CS_false
   initialize to Keep_Control
   set   WE_bar      to "1"
   set   CS_bar      to "1"
end vector

vector   Tristate
   set   CS_bar         to "z"
!#####   User modification required   #####
!! set   Disablegroup   to "z"
end vector

vector   Array_Keep_Control
   set   CS_bar      to "k"
end vector

vector   Store_false
   initialize to Keep_Control
   set   Store_bar   to "1"
end vector

vector   Store_true
   initialize to Keep_Control
   set   WE_bar      to "1"
   set   Store_bar   to "0"
end vector

vector   Array_Recall_false
   initialize to Keep_Control
   set   Array_Recall_bar  to "1"
end vector

vector   Array_Recall_true
   initialize to Keep_Control
   set   WE_bar      to "1"
   set   Array_Recall_bar  to "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   Initialize_IO1
   drive IO1
   set   IO1      to "0"
   set   A5_A0    to "000000"
   set   CS_bar   to "0"
   set   WE_bar   to "1"
   set   Store_bar         to "1"
   set   Array_Recall_bar  to "1"
end vector

vector   Keep_Control_IO1
   drive IO1
   set   IO1      to "k"
   set   A5_A0    to "kkkkkk"
   set   CS_bar   to "k"
   set   WE_bar   to "k"
   set   Store_bar         to "k"
   set   Array_Recall_bar  to "k"
end vector

vector   End_Cycle_IO1
   drive IO1
   set   IO1      to "k"
   set   A5_A0    to "kkkkkk"
   set   CS_bar   to "k"
   set   WE_bar   to "0"
   set   Store_bar         to "k"
   set   Array_Recall_bar  to "k"
end vector

vector   Add_000000_IO1
   initialize to Keep_Control_IO1
   set   WE_bar   to "1"
   set   A5_A0    to "000000"
end vector

vector   Data_IO1_0D
   initialize to Keep_Control_IO1
   set   IO1      to "0"
end vector

vector   Data_IO1_1D
   initialize to Keep_Control_IO1
   set   IO1      to "1"
end vector

vector   Data_IO1_0R
   initialize to Keep_Control_IO1
   receive  IO1
   set   IO1      to "0"
end vector

vector   Data_IO1_1R
   initialize to Keep_Control_IO1
   receive  IO1
   set   IO1      to "1"
end vector

vector   Initialize_IO2
   drive IO2
   set   IO2      to "0"
   set   A5_A0    to "000000"
   set   CS_bar   to "0"
   set   WE_bar   to "1"
   set   Store_bar         to "1"
   set   Array_Recall_bar  to "1"
end vector

vector   Keep_Control_IO2
   drive IO2
   set   IO2      to "k"
   set   A5_A0    to "kkkkkk"
   set   CS_bar   to "k"
   set   WE_bar   to "k"
   set   Store_bar         to "k"
   set   Array_Recall_bar  to "k"
end vector

vector   End_Cycle_IO2
   drive IO2
   set   IO2      to "k"
   set   A5_A0    to "kkkkkk"
   set   CS_bar   to "k"
   set   WE_bar   to "0"
   set   Store_bar         to "k"
   set   Array_Recall_bar  to "k"
end vector

vector   Add_000000_IO2
   initialize to Keep_Control_IO2
   set   WE_bar   to "1"
   set   A5_A0    to "000000"
end vector

vector   Data_IO2_0D
   initialize to Keep_Control_IO2
   set   IO2      to "0"
end vector

vector   Data_IO2_1D
   initialize to Keep_Control_IO2
   set   IO2      to "1"
end vector

vector   Data_IO2_0R
   initialize to Keep_Control_IO2
   receive  IO2
   set   IO2      to "0"
end vector

vector   Data_IO2_1R
   initialize to Keep_Control_IO2
   receive  IO2
   set   IO2      to "1"
end vector

vector   Initialize_IO3
   drive IO3
   set   IO3      to "0"
   set   A5_A0    to "000000"
   set   CS_bar   to "0"
   set   WE_bar   to "1"
   set   Store_bar         to "1"
   set   Array_Recall_bar  to "1"
end vector

vector   Keep_Control_IO3
   drive IO3
   set   IO3      to "k"
   set   A5_A0    to "kkkkkk"
   set   CS_bar   to "k"
   set   WE_bar   to "k"
   set   Store_bar         to "k"
   set   Array_Recall_bar  to "k"
end vector

vector   End_Cycle_IO3
   drive IO3
   set   IO3      to "k"
   set   A5_A0    to "kkkkkk"
   set   CS_bar   to "k"
   set   WE_bar   to "0"
   set   Store_bar         to "k"
   set   Array_Recall_bar  to "k"
end vector

vector   Add_000000_IO3
   initialize to Keep_Control_IO3
   set   WE_bar   to "1"
   set   A5_A0    to "000000"
end vector

vector   Data_IO3_0D
   initialize to Keep_Control_IO3
   set   IO3      to "0"
end vector

vector   Data_IO3_1D
   initialize to Keep_Control_IO3
   set   IO3      to "1"
end vector

vector   Data_IO3_0R
   initialize to Keep_Control_IO3
   receive  IO3
   set   IO3      to "0"
end vector

vector   Data_IO3_1R
   initialize to Keep_Control_IO3
   receive  IO3
   set   IO3      to "1"
end vector

vector   Initialize_IO4
   drive IO4
   set   IO4      to "0"
   set   A5_A0    to "000000"
   set   CS_bar   to "0"
   set   WE_bar   to "1"
   set   Store_bar         to "1"
   set   Array_Recall_bar  to "1"
end vector

vector   Keep_Control_IO4
   drive IO4
   set   IO4      to "k"
   set   A5_A0    to "kkkkkk"
   set   CS_bar   to "k"
   set   WE_bar   to "k"
   set   Store_bar         to "k"
   set   Array_Recall_bar  to "k"
end vector

vector   End_Cycle_IO4
   drive IO4
   set   IO4      to "k"
   set   A5_A0    to "kkkkkk"
   set   CS_bar   to "k"
   set   WE_bar   to "0"
   set   Store_bar         to "k"
   set   Array_Recall_bar  to "k"
end vector

vector   Add_000000_IO4
   initialize to Keep_Control_IO4
   set   WE_bar   to "1"
   set   A5_A0    to "000000"
end vector

vector   Data_IO4_0D
   initialize to Keep_Control_IO4
   set   IO4      to "0"
end vector

vector   Data_IO4_1D
   initialize to Keep_Control_IO4
   set   IO4      to "1"
end vector

vector   Data_IO4_0R
   initialize to Keep_Control_IO4
   receive  IO4
   set   IO4      to "0"
end vector

vector   Data_IO4_1R
   initialize to Keep_Control_IO4
   receive  IO4
   set   IO4      to "1"
end vector


!
!*******************************************************************************
!

sub   Write_cycle(Address, Data)
   execute  Address
   execute  Data
   execute  End_cycle
end sub

sub   Read_cycle(Address, Data)
   execute  Address
   execute  Data
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_cycle" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_cycle" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_cycle_Dx (Address, Data, End_cycle)
   execute  Address
   execute  Data
   execute  End_cycle
end sub

!
!*******************************************************************************
!

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with IO1.

unit   "awaretest IO1 Test"

   execute  Initialize_IO1

   call Write_cycle_Dx (Add_000000_IO1, Data_IO1_0D, End_cycle_IO1)
   call Read_cycle  (Add_000000_IO1, Data_IO1_0R)

   call Write_cycle_Dx (Add_000000_IO1, Data_IO1_1D, End_cycle_IO1)
   call Read_cycle  (Add_000000_IO1, Data_IO1_1R)

end unit

unit   "awaretest IO2 Test"

   execute  Initialize_IO2

   call Write_cycle_Dx (Add_000000_IO2, Data_IO2_0D, End_cycle_IO2)
   call Read_cycle  (Add_000000_IO2, Data_IO2_0R)

   call Write_cycle_Dx (Add_000000_IO2, Data_IO2_1D, End_cycle_IO2)
   call Read_cycle  (Add_000000_IO2, Data_IO2_1R)

end unit

unit   "awaretest IO3 Test"

   execute  Initialize_IO3

   call Write_cycle_Dx (Add_000000_IO3, Data_IO3_0D, End_cycle_IO3)
   call Read_cycle  (Add_000000_IO3, Data_IO3_0R)

   call Write_cycle_Dx (Add_000000_IO3, Data_IO3_1D, End_cycle_IO3)
   call Read_cycle  (Add_000000_IO3, Data_IO3_1R)

end unit

unit   "awaretest IO4 Test"

   execute  Initialize_IO4

   call Write_cycle_Dx (Add_000000_IO4, Data_IO4_0D, End_cycle_IO4)
   call Read_cycle  (Add_000000_IO4, Data_IO4_0R)

   call Write_cycle_Dx (Add_000000_IO4, Data_IO4_1D, End_cycle_IO4)
   call Read_cycle  (Add_000000_IO4, Data_IO4_1R)

end unit

unit "Test Address and Data Pins"
   execute  Initialize

   call Write_cycle (Add_000000, Data_0101D)
   call Write_cycle (Add_000001, Data_0101D)
   call Write_cycle (Add_000010, Data_0101D)
   call Write_cycle (Add_000100, Data_0101D)
   call Write_cycle (Add_001000, Data_0101D)
   call Write_cycle (Add_010000, Data_0101D)
   call Write_cycle (Add_100000, Data_0101D)

   call Read_cycle  (Add_000000, Data_0101R)
   call Write_cycle (Add_000000, Data_1010D)
   call Read_cycle  (Add_000001, Data_0101R)
   call Write_cycle (Add_000001, Data_1010D)
   call Read_cycle  (Add_000010, Data_0101R)
   call Write_cycle (Add_000010, Data_1010D)
   call Read_cycle  (Add_000100, Data_0101R)
   call Write_cycle (Add_000100, Data_1010D)
   call Read_cycle  (Add_001000, Data_0101R)
   call Write_cycle (Add_001000, Data_1010D)
   call Read_cycle  (Add_010000, Data_0101R)
   call Write_cycle (Add_010000, Data_1010D)
   call Read_cycle  (Add_100000, Data_0101R)
   call Write_cycle (Add_100000, Data_1010D)

   call Read_cycle  (Add_000000, Data_1010R)
   call Read_cycle  (Add_000001, Data_1010R)
   call Read_cycle  (Add_000010, Data_1010R)
   call Read_cycle  (Add_000100, Data_1010R)
   call Read_cycle  (Add_001000, Data_1010R)
   call Read_cycle  (Add_010000, Data_1010R)
   call Read_cycle  (Add_100000, Data_1010R)
end unit

unit "Test Chip Select"
   execute  Initialize

   call Write_cycle (Add_000000, Data_1010D)
   execute  CS_false
   call Write_cycle (Add_000000, Data_0101D)
   execute  CS_true
   call Read_cycle  (Add_000000, Data_1010R)
end unit

unit "Test Nonvolatile Memory"

   execute  Initialize

   call Write_cycle (Add_000000, Data_0101D)
   call Write_cycle (Add_111111, Data_1010D)

   execute  Store_true
   execute  Store_false

   repeat 10 times                       ! 10ms delay needed
      repeat 100 times                   ! 100 10us periods in 1ms
         execute  Tristate     ! 5us
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate

         execute  Tristate     ! 5us
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
      end repeat
   end repeat

   execute Initialize

   call Write_cycle (Add_000000, Data_1010D)
   call Write_cycle (Add_111111, Data_0101D)

   execute  Array_Recall_true
   execute  Array_Recall_false

   execute  Array_Keep_Control         ! 1us delay
   execute  Array_Keep_Control

   call Read_cycle  (Add_000000, Data_0101R)
   call Read_cycle  (Add_111111, Data_1010R)

   call Write_cycle (Add_000000, Data_1010D)
   call Write_cycle (Add_111111, Data_0101D)

   execute  Store_true
   execute  Store_false

   repeat 10 times                       ! 10ms delay needed
      repeat 100 times                   ! 100 10us periods in 1ms
         execute  Tristate     ! 5us
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate

         execute  Tristate     ! 5us
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
         execute  Tristate
      end repeat
   end repeat

   execute  Initialize

   call Write_cycle (Add_000000, Data_0101D)
   call Write_cycle (Add_111111, Data_1010D)

   execute  Array_Recall_true
   execute  Array_Recall_false

   execute  Array_Keep_Control         ! 1us delay
   execute  Array_Keep_Control

   call Read_cycle  (Add_000000, Data_1010R)
   call Read_cycle  (Add_111111, Data_0101R)
end unit

! End Test