!!!!    6    0    1  986843569  V9df1                                         

! Device           : 2186
! Function         : RAM,  2048 x 8    Integrated Ram
! revision         : B.01.00
! safeguard        : standard_lttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

assign  VCC     to pins 28
assign  GND     to pins 14

vector cycle  500n
receive delay 400n

assign  Address_Bus         to pins 2,23,21,25,24,3,4,5,6
assign  Address_Bus         to pins 7,8,9,10
assign  Data_Bus            to pins 19,18,17,16,15,13,12,11
assign  Data_D0             to pins 11   !AT Added for minimum pin test.
assign  Data_D1             to pins 12   !AT Added for minimum pin test.
assign  Data_D2             to pins 13   !AT Added for minimum pin test.
assign  Data_D3             to pins 15   !AT Added for minimum pin test.
assign  Data_D4             to pins 16   !AT Added for minimum pin test.
assign  Data_D5             to pins 17   !AT Added for minimum pin test.
assign  Data_D6             to pins 18   !AT Added for minimum pin test.
assign  Data_D7             to pins 19   !AT Added for minimum pin test.

assign  Chip_Enable_bar     to pins 20
assign  Output_Enable_bar   to pins 22
assign  Write_Enable_bar    to pins 27
assign  NC                  to pins 26
assign  Ready               to pins 1  ! Open Drain
                                       ! Normally connected to VCC.
family  TTL

power   VCC, GND

inputs  Address_Bus, Chip_Enable_bar, Output_Enable_bar
inputs  Write_Enable_bar

format  hexadecimal  Address_Bus, Data_Bus

bidirectional  Data_Bus
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.
bidirectional  Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test.

nondigital  NC, Ready

set load on groups Data_Bus      to pull up

when     Chip_Enable_bar   is    "1"   inactive Data_bus
when     Output_Enable_bar is    "1"   inactive Data_bus

when     Write_Enable_bar  is    "0"   inputs   Data_bus
when     Write_Enable_bar  is    "1"   outputs  Data_bus

trace    Data_bus   to  Write_Enable_bar,Address_Bus
trace    Data_bus   to  Chip_Enable_bar,Output_Enable_bar

disable  Data_Bus   with   Chip_Enable_bar   to    "1"
disable  Data_Bus   with   Output_Enable_bar to    "1"

!*****************************************************************************
!*****************************************************************************

vector  Initialize_Controls
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "1"
end vector

vector  Chip_Enable_true
  set  Output_Enable_bar    to "k"
  set  Write_Enable_bar     to "k"
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "0"
end vector

vector  Chip_Enable_false
  set  Output_Enable_bar    to "k"
  set  Write_Enable_bar     to "k"
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "1"
end vector

vector  Write_Enable_true
  drive Data_Bus
  set  Chip_Enable_bar      to "k"
  set  Output_Enable_bar    to "k"
  set  Address_Bus          to "kkkk"
  set  Data_Bus             to "kk"
  set  Write_Enable_bar     to "0"
end vector

vector  Read_Enable_true
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "k"
  set  Write_Enable_bar     to "k"
  set  Output_Enable_bar    to "0"
end vector

vector  Write_Disabled
  drive Data_Bus
  set  Address_Bus          to "kkkk"
  set  Data_Bus             to "kk"
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "1"
end vector

vector  Read_Disabled
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "k"
end vector

vector  Data_In_03_CE
  initialize to Chip_Enable_false
  drive Data_bus
  set  Data_bus     to "03"
end vector

vector  Address_0000
  initialize to Initialize_Controls
  set  Address_bus  to "0000"
end vector

vector  Address_0001
  initialize to Initialize_Controls
  set  Address_bus  to "0001"
end vector

vector  Address_0003
  initialize to Initialize_Controls
  set  Address_bus  to "0003"
end vector

vector  Address_0007
  initialize to Initialize_Controls
  set  Address_bus  to "0007"
end vector

vector  Address_000F
  initialize to Initialize_Controls
  set  Address_bus  to "000F"
end vector

vector  Address_001F
  initialize to Initialize_Controls
  set  Address_bus  to "001F"
end vector

vector  Address_003F
  initialize to Initialize_Controls
  set  Address_bus  to "003F"
end vector

vector  Address_007F
  initialize to Initialize_Controls
  set  Address_bus  to "007F"
end vector

vector  Address_00FF
  initialize to Initialize_Controls
  set  Address_bus  to "00FF"
end vector

vector  Address_01FF
  initialize to Initialize_Controls
  set  Address_bus  to "01FF"
end vector

vector  Address_03FF
  initialize to Initialize_Controls
  set  Address_bus  to "03FF"
end vector

vector  Address_07FF
  initialize to Initialize_Controls
  set  Address_bus  to "07FF"
end vector

vector  Address_0FFF
  initialize to Initialize_Controls
  set  Address_bus  to "0FFF"
end vector

vector  Address_1FFF
  initialize to Initialize_Controls
  set  Address_bus  to "1FFF"
end vector

vector  Data_In_01
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "01"
end vector

vector  Data_In_03
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "03"
end vector

vector  Data_In_07
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "07"
end vector

vector  Data_In_0F
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "0F"
end vector

vector  Data_In_1F
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "1F"
end vector

vector  Data_In_3F
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "3F"
end vector

vector  Data_In_7F
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "7F"
end vector

vector  Data_In_FF
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "FF"
end vector

vector  Data_In_FE
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "FE"
end vector

vector  Data_In_FD
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "FD"
end vector

vector  Data_In_FB
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "FB"
end vector

vector  Data_In_F7
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "F7"
end vector

vector  Data_In_EF
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "EF"
end vector

vector  Data_In_DF
  initialize to Chip_Enable_true
  drive Data_bus
  set  Data_bus     to "DF"
end vector

vector  Data_Out_01
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "01"
end vector

vector  Data_Out_03
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "03"
end vector

vector  Data_Out_07
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "07"
end vector

vector  Data_Out_0F
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "0F"
end vector

vector  Data_Out_1F
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "1F"
end vector

vector  Data_Out_3F
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "3F"
end vector

vector  Data_Out_7F
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "7F"
end vector

vector  Data_Out_FF
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "FF"
end vector

vector  Data_Out_FE
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "FE"
end vector

vector  Data_Out_FD
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "FD"
end vector

vector  Data_Out_FB
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "FB"
end vector

vector  Data_Out_F7
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "F7"
end vector

vector  Data_Out_EF
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "EF"
end vector

vector  Data_Out_DF
  initialize to Chip_Enable_true
  receive Data_bus
  set  Data_bus     to "DF"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  WEb_lo_D0
  drive Data_D0
  set  Chip_Enable_bar      to "k"
  set  Output_Enable_bar    to "k"
  set  Data_D0              to "k"
  set  Address_Bus          to "kkkk"
  set  Write_Enable_bar     to "0"
end vector

vector  WEb_lo_D1
  drive Data_D1
  set  Chip_Enable_bar      to "k"
  set  Output_Enable_bar    to "k"
  set  Data_D1              to "k"
  set  Address_Bus          to "kkkk"
  set  Write_Enable_bar     to "0"
end vector

vector  WEb_lo_D2
  drive Data_D2
  set  Chip_Enable_bar      to "k"
  set  Output_Enable_bar    to "k"
  set  Data_D2              to "k"
  set  Address_Bus          to "kkkk"
  set  Write_Enable_bar     to "0"
end vector

vector  WEb_lo_D3
  drive Data_D3
  set  Chip_Enable_bar      to "k"
  set  Output_Enable_bar    to "k"
  set  Data_D3              to "k"
  set  Address_Bus          to "kkkk"
  set  Write_Enable_bar     to "0"
end vector

vector  WEb_lo_D4
  drive Data_D4
  set  Chip_Enable_bar      to "k"
  set  Output_Enable_bar    to "k"
  set  Data_D4              to "k"
  set  Address_Bus          to "kkkk"
  set  Write_Enable_bar     to "0"
end vector

vector  WEb_lo_D5
  drive Data_D5
  set  Chip_Enable_bar      to "k"
  set  Output_Enable_bar    to "k"
  set  Data_D5              to "k"
  set  Address_Bus          to "kkkk"
  set  Write_Enable_bar     to "0"
end vector

vector  WEb_lo_D6
  drive Data_D6
  set  Chip_Enable_bar      to "k"
  set  Output_Enable_bar    to "k"
  set  Data_D6              to "k"
  set  Address_Bus          to "kkkk"
  set  Write_Enable_bar     to "0"
end vector

vector  WEb_lo_D7
  drive Data_D7
  set  Chip_Enable_bar      to "k"
  set  Output_Enable_bar    to "k"
  set  Data_D7              to "k"
  set  Address_Bus          to "kkkk"
  set  Write_Enable_bar     to "0"
end vector

vector  WEb_hi_D0
  drive Data_D0
  set  Data_D0              to "k"
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "1"
end vector

vector  WEb_hi_D1
  drive Data_D1
  set  Data_D1              to "k"
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "1"
end vector

vector  WEb_hi_D2
  drive Data_D2
  set  Data_D2              to "k"
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "1"
end vector

vector  WEb_hi_D3
  drive Data_D3
  set  Data_D3              to "k"
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "1"
end vector

vector  WEb_hi_D4
  drive Data_D4
  set  Data_D4              to "k"
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "1"
end vector

vector  WEb_hi_D5
  drive Data_D5
  set  Data_D5              to "k"
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "1"
end vector

vector  WEb_hi_D6
  drive Data_D6
  set  Data_D6              to "k"
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "1"
end vector

vector  WEb_hi_D7
  drive Data_D7
  set  Data_D7              to "k"
  set  Address_Bus          to "kkkk"
  set  Chip_Enable_bar      to "1"
  set  Output_Enable_bar    to "1"
  set  Write_Enable_bar     to "1"
end vector

vector  Data_In_D0_0
  initialize to Chip_Enable_true
  drive Data_D0
  set  Data_D0      to "0"
end vector

vector  Data_In_D0_1
  initialize to Chip_Enable_true
  drive Data_D0
  set  Data_D0      to "1"
end vector

vector  Data_In_D1_0
  initialize to Chip_Enable_true
  drive Data_D1
  set  Data_D1      to "0"
end vector

vector  Data_In_D1_1
  initialize to Chip_Enable_true
  drive Data_D1
  set  Data_D1      to "1"
end vector

vector  Data_In_D2_0
  initialize to Chip_Enable_true
  drive Data_D2
  set  Data_D2      to "0"
end vector

vector  Data_In_D2_1
  initialize to Chip_Enable_true
  drive Data_D2
  set  Data_D2      to "1"
end vector

vector  Data_In_D3_0
  initialize to Chip_Enable_true
  drive Data_D3
  set  Data_D3      to "0"
end vector

vector  Data_In_D3_1
  initialize to Chip_Enable_true
  drive Data_D3
  set  Data_D3      to "1"
end vector

vector  Data_In_D4_0
  initialize to Chip_Enable_true
  drive Data_D4
  set  Data_D4      to "0"
end vector

vector  Data_In_D4_1
  initialize to Chip_Enable_true
  drive Data_D4
  set  Data_D4      to "1"
end vector

vector  Data_In_D5_0
  initialize to Chip_Enable_true
  drive Data_D5
  set  Data_D5      to "0"
end vector

vector  Data_In_D5_1
  initialize to Chip_Enable_true
  drive Data_D5
  set  Data_D5      to "1"
end vector

vector  Data_In_D6_0
  initialize to Chip_Enable_true
  drive Data_D6
  set  Data_D6      to "0"
end vector

vector  Data_In_D6_1
  initialize to Chip_Enable_true
  drive Data_D6
  set  Data_D6      to "1"
end vector

vector  Data_In_D7_0
  initialize to Chip_Enable_true
  drive Data_D7
  set  Data_D7      to "0"
end vector

vector  Data_In_D7_1
  initialize to Chip_Enable_true
  drive Data_D7
  set  Data_D7      to "1"
end vector

vector  Data_Out_D0_0
  initialize to Chip_Enable_true
  receive Data_D0
  set  Data_D0      to "0"
end vector

vector  Data_Out_D0_1
  initialize to Chip_Enable_true
  receive Data_D0
  set  Data_D0      to "1"
end vector

vector  Data_Out_D1_0
  initialize to Chip_Enable_true
  receive Data_D1
  set  Data_D1      to "0"
end vector

vector  Data_Out_D1_1
  initialize to Chip_Enable_true
  receive Data_D1
  set  Data_D1      to "1"
end vector

vector  Data_Out_D2_0
  initialize to Chip_Enable_true
  receive Data_D2
  set  Data_D2      to "0"
end vector

vector  Data_Out_D2_1
  initialize to Chip_Enable_true
  receive Data_D2
  set  Data_D2      to "1"
end vector

vector  Data_Out_D3_0
  initialize to Chip_Enable_true
  receive Data_D3
  set  Data_D3      to "0"
end vector

vector  Data_Out_D3_1
  initialize to Chip_Enable_true
  receive Data_D3
  set  Data_D3      to "1"
end vector

vector  Data_Out_D4_0
  initialize to Chip_Enable_true
  receive Data_D4
  set  Data_D4      to "0"
end vector

vector  Data_Out_D4_1
  initialize to Chip_Enable_true
  receive Data_D4
  set  Data_D4      to "1"
end vector

vector  Data_Out_D5_0
  initialize to Chip_Enable_true
  receive Data_D5
  set  Data_D5      to "0"
end vector

vector  Data_Out_D5_1
  initialize to Chip_Enable_true
  receive Data_D5
  set  Data_D5      to "1"
end vector

vector  Data_Out_D6_0
  initialize to Chip_Enable_true
  receive Data_D6
  set  Data_D6      to "0"
end vector

vector  Data_Out_D6_1
  initialize to Chip_Enable_true
  receive Data_D6
  set  Data_D6      to "1"
end vector

vector  Data_Out_D7_0
  initialize to Chip_Enable_true
  receive Data_D7
  set  Data_D7      to "0"
end vector

vector  Data_Out_D7_1
  initialize to Chip_Enable_true
  receive Data_D7
  set  Data_D7      to "1"
end vector

!*****************************************************************************
!*****************************************************************************

sub  Refresh
  repeat 128 times
  execute  Address_0000
  execute  Chip_Enable_true
  execute  Data_In_01
  execute  Write_Enable_true
  execute  Write_Disabled
  end repeat
end sub

sub  Write_Data (Address,Data)
  execute  Address
  execute  Chip_Enable_true
  execute  Data
  execute  Write_Enable_true
  execute  Write_Disabled
end sub

sub  Read_Data (Address,Data)
  execute  Address
  execute  Chip_Enable_true
  execute  Read_enable_true
  execute  Data
  execute  Read_Disabled
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, WEb_lo_Dx, WEb_hi_Dx)
  execute  Address
  execute  Chip_Enable_true
  execute  Data_Dx
  execute  WEb_lo_Dx
  execute  WEb_hi_Dx
end sub

!*****************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

     repeat 128 times
        call Write_data_Dx (Address_0000, Data_In_D0_0, WEb_lo_D0, WEb_hi_D0)
     end repeat

     call Write_data_Dx (Address_0000, Data_In_D0_0, WEb_lo_D0, WEb_hi_D0)
     call Read_Data (Address_0000, Data_Out_D0_0)

     call Write_data_Dx (Address_0000, Data_In_D0_1, WEb_lo_D0, WEb_hi_D0)
     call Read_Data (Address_0000, Data_Out_D0_1)

end unit

unit   "awaretest D1 Test"

     repeat 128 times
        call Write_data_Dx (Address_0000, Data_In_D1_0, WEb_lo_D1, WEb_hi_D1)
     end repeat

     call Write_data_Dx (Address_0000, Data_In_D1_0, WEb_lo_D1, WEb_hi_D1)
     call Read_Data (Address_0000, Data_Out_D1_0)

     call Write_data_Dx (Address_0000, Data_In_D1_1, WEb_lo_D1, WEb_hi_D1)
     call Read_Data (Address_0000, Data_Out_D1_1)

end unit

unit   "awaretest D2 Test"

     repeat 128 times
        call Write_data_Dx (Address_0000, Data_In_D2_0, WEb_lo_D2, WEb_hi_D2)
     end repeat

     call Write_data_Dx (Address_0000, Data_In_D2_0, WEb_lo_D2, WEb_hi_D2)
     call Read_Data (Address_0000, Data_Out_D2_0)

     call Write_data_Dx (Address_0000, Data_In_D2_1, WEb_lo_D2, WEb_hi_D2)
     call Read_Data (Address_0000, Data_Out_D2_1)

end unit

unit   "awaretest D3 Test"

     repeat 128 times
        call Write_data_Dx (Address_0000, Data_In_D3_0, WEb_lo_D3, WEb_hi_D3)
     end repeat

     call Write_data_Dx (Address_0000, Data_In_D3_0, WEb_lo_D3, WEb_hi_D3)
     call Read_Data (Address_0000, Data_Out_D3_0)

     call Write_data_Dx (Address_0000, Data_In_D3_1, WEb_lo_D3, WEb_hi_D3)
     call Read_Data (Address_0000, Data_Out_D3_1)

end unit

unit   "awaretest D4 Test"

     repeat 128 times
        call Write_data_Dx (Address_0000, Data_In_D4_0, WEb_lo_D4, WEb_hi_D4)
     end repeat

     call Write_data_Dx (Address_0000, Data_In_D4_0, WEb_lo_D4, WEb_hi_D4)
     call Read_Data (Address_0000, Data_Out_D4_0)

     call Write_data_Dx (Address_0000, Data_In_D4_1, WEb_lo_D4, WEb_hi_D4)
     call Read_Data (Address_0000, Data_Out_D4_1)

end unit

unit   "awaretest D5 Test"

     repeat 128 times
        call Write_data_Dx (Address_0000, Data_In_D5_0, WEb_lo_D5, WEb_hi_D5)
     end repeat

     call Write_data_Dx (Address_0000, Data_In_D5_0, WEb_lo_D5, WEb_hi_D5)
     call Read_Data (Address_0000, Data_Out_D5_0)

     call Write_data_Dx (Address_0000, Data_In_D5_1, WEb_lo_D5, WEb_hi_D5)
     call Read_Data (Address_0000, Data_Out_D5_1)

end unit

unit   "awaretest D6 Test"

     repeat 128 times
        call Write_data_Dx (Address_0000, Data_In_D6_0, WEb_lo_D6, WEb_hi_D6)
     end repeat

     call Write_data_Dx (Address_0000, Data_In_D6_0, WEb_lo_D6, WEb_hi_D6)
     call Read_Data (Address_0000, Data_Out_D6_0)

     call Write_data_Dx (Address_0000, Data_In_D6_1, WEb_lo_D6, WEb_hi_D6)
     call Read_Data (Address_0000, Data_Out_D6_1)

end unit

unit   "awaretest D7 Test"

     repeat 128 times
        call Write_data_Dx (Address_0000, Data_In_D7_0, WEb_lo_D7, WEb_hi_D7)
     end repeat

     call Write_data_Dx (Address_0000, Data_In_D7_0, WEb_lo_D7, WEb_hi_D7)
     call Read_Data (Address_0000, Data_Out_D7_0)

     call Write_data_Dx (Address_0000, Data_In_D7_1, WEb_lo_D7, WEb_hi_D7)
     call Read_Data (Address_0000, Data_Out_D7_1)

end unit

unit "Ram_Test"
  call Refresh
  call Write_Data (Address_0001,Data_In_01)
  call Write_Data (Address_0003,Data_In_03)
  call Write_Data (Address_0007,Data_In_07)
  call Write_Data (Address_000F,Data_In_0F)
  call Write_Data (Address_001F,Data_In_1F)
  call Write_Data (Address_003F,Data_In_3F)
  call Write_Data (Address_007F,Data_In_7F)
  call Write_Data (Address_00FF,Data_In_FF)
  call Write_Data (Address_01FF,Data_In_FE)
  call Write_Data (Address_03FF,Data_In_FD)
  call Write_Data (Address_07FF,Data_In_FB)
  call Write_Data (Address_0FFF,Data_In_F7)
  call Write_Data (Address_1FFF,Data_In_EF)
  call Write_Data (Address_0000,Data_In_DF)

  call Read_Data (Address_0001,Data_Out_01)
  call Read_Data (Address_0003,Data_Out_03)
  call Read_Data (Address_0007,Data_Out_07)
  call Read_Data (Address_000F,Data_Out_0F)
  call Read_Data (Address_001F,Data_Out_1F)
  call Read_Data (Address_003F,Data_Out_3F)
  call Read_Data (Address_007F,Data_Out_7F)
  call Read_Data (Address_00FF,Data_Out_FF)
  call Read_Data (Address_01FF,Data_Out_FE)
  call Read_Data (Address_03FF,Data_Out_FD)
  call Read_Data (Address_07FF,Data_Out_FB)
  call Read_Data (Address_0FFF,Data_Out_F7)
  call Read_Data (Address_1FFF,Data_Out_EF)
  call Read_Data (Address_0000,Data_Out_DF)
  call Write_Data (Address_0001,Data_In_FE)
end unit

unit "Test_Chip_Enable"
  call Write_Data (Address_0001,Data_In_01)
  execute  Address_0001
  execute  Chip_Enable_false
  execute  Data_In_03_CE
  execute  Write_Enable_true
  execute  Write_Disabled
  call Read_Data (Address_0001,Data_Out_01)
end unit

unit "Test_Write_Enable"
  call Write_Data (Address_0000,Data_In_03)
  execute  Address_0000
  execute  Chip_Enable_true
  execute  Data_In_01
  execute  Write_Disabled
  call Read_Data (Address_0000,Data_Out_03)
end unit

!     End of test